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[LV][EVL] Attach a new metadata on EVL vectorized loops (llvm#131000)
This patch attaches a new metadata, `llvm.loop.isvectorized.withevl`, on loops vectorized with explicit vector length. This will help other optimizations down in the pipeline that focus on EVL-vectorized loop This approach is much safer than, said IR pattern matching to figure out if a loop is EVL-vectorized or not.
1 parent 009b9f4 commit e0537c0

15 files changed

+301
-269
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7926,6 +7926,26 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
79267926

79277927
LoopVectorizeHints Hints(L, true, *ORE);
79287928
Hints.setAlreadyVectorized();
7929+
7930+
// Check if it's EVL-vectorized and mark the corresponding metadata.
7931+
bool IsEVLVectorized =
7932+
llvm::any_of(*HeaderVPBB, [](const VPRecipeBase &Recipe) {
7933+
// Looking for the ExplictVectorLength VPInstruction.
7934+
if (const auto *VI = dyn_cast<VPInstruction>(&Recipe))
7935+
return VI->getOpcode() == VPInstruction::ExplicitVectorLength;
7936+
return false;
7937+
});
7938+
if (IsEVLVectorized) {
7939+
LLVMContext &Context = L->getHeader()->getContext();
7940+
MDNode *LoopID = L->getLoopID();
7941+
auto *IsEVLVectorizedMD = MDNode::get(
7942+
Context,
7943+
{MDString::get(Context, "llvm.loop.isvectorized.tailfoldingstyle"),
7944+
MDString::get(Context, "evl")});
7945+
MDNode *NewLoopID = makePostTransformationMetadata(Context, LoopID, {},
7946+
{IsEVLVectorizedMD});
7947+
L->setLoopID(NewLoopID);
7948+
}
79297949
}
79307950
TargetTransformInfo::UnrollingPreferences UP;
79317951
TTI.getUnrollingPreferences(L, *PSE.getSE(), UP, ORE);

‎llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %src) {
5454
; CHECK-NEXT: store i8 [[CONV36]], ptr null, align 1
5555
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
5656
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV1]], 8
57-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
57+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
5858
; CHECK: [[EXIT]]:
5959
; CHECK-NEXT: ret void
6060
;
@@ -78,8 +78,9 @@ exit: ; preds = %loop
7878
ret void
7979
}
8080
;.
81-
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
81+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
8282
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
83-
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
84-
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
83+
; CHECK: [[META2]] = !{!"llvm.loop.isvectorized.tailfoldingstyle", !"evl"}
84+
; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
85+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]], [[META1]]}
8586
;.

‎llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ define void @type_info_cache_clobber(ptr %dstv, ptr %src, i64 %wide.trip.count)
7979
; CHECK-NEXT: store i16 [[CONV36]], ptr null, align 2
8080
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
8181
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[WIDE_TRIP_COUNT]]
82-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
82+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
8383
; CHECK: [[EXIT]]:
8484
; CHECK-NEXT: ret void
8585
;
@@ -113,8 +113,9 @@ exit:
113113
; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}
114114
; CHECK: [[META3]] = !{[[META4:![0-9]+]]}
115115
; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}
116-
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
116+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]], [[META8:![0-9]+]]}
117117
; CHECK: [[META6]] = !{!"llvm.loop.isvectorized", i32 1}
118-
; CHECK: [[META7]] = !{!"llvm.loop.unroll.runtime.disable"}
119-
; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META6]]}
118+
; CHECK: [[META7]] = !{!"llvm.loop.isvectorized.tailfoldingstyle", !"evl"}
119+
; CHECK: [[META8]] = !{!"llvm.loop.unroll.runtime.disable"}
120+
; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META6]]}
120121
;.

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll‎

Lines changed: 73 additions & 72 deletions
Large diffs are not rendered by default.

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll‎

Lines changed: 37 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ define void @vp_smax(ptr %a, ptr %b, ptr %c, i64 %N) {
7979
; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4
8080
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
8181
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
82-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
82+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
8383
; IF-EVL: [[EXIT]]:
8484
; IF-EVL-NEXT: ret void
8585
;
@@ -176,7 +176,7 @@ define void @vp_smin(ptr %a, ptr %b, ptr %c, i64 %N) {
176176
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
177177
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
178178
; IF-EVL-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
179-
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
179+
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
180180
; IF-EVL: [[MIDDLE_BLOCK]]:
181181
; IF-EVL-NEXT: br label %[[EXIT:.*]]
182182
; IF-EVL: [[SCALAR_PH]]:
@@ -193,7 +193,7 @@ define void @vp_smin(ptr %a, ptr %b, ptr %c, i64 %N) {
193193
; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4
194194
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
195195
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
196-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
196+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
197197
; IF-EVL: [[EXIT]]:
198198
; IF-EVL-NEXT: ret void
199199
;
@@ -290,7 +290,7 @@ define void @vp_umax(ptr %a, ptr %b, ptr %c, i64 %N) {
290290
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
291291
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
292292
; IF-EVL-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
293-
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
293+
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
294294
; IF-EVL: [[MIDDLE_BLOCK]]:
295295
; IF-EVL-NEXT: br label %[[EXIT:.*]]
296296
; IF-EVL: [[SCALAR_PH]]:
@@ -307,7 +307,7 @@ define void @vp_umax(ptr %a, ptr %b, ptr %c, i64 %N) {
307307
; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4
308308
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
309309
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
310-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
310+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
311311
; IF-EVL: [[EXIT]]:
312312
; IF-EVL-NEXT: ret void
313313
;
@@ -404,7 +404,7 @@ define void @vp_umin(ptr %a, ptr %b, ptr %c, i64 %N) {
404404
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
405405
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
406406
; IF-EVL-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
407-
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
407+
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
408408
; IF-EVL: [[MIDDLE_BLOCK]]:
409409
; IF-EVL-NEXT: br label %[[EXIT:.*]]
410410
; IF-EVL: [[SCALAR_PH]]:
@@ -421,7 +421,7 @@ define void @vp_umin(ptr %a, ptr %b, ptr %c, i64 %N) {
421421
; IF-EVL-NEXT: store i32 [[DOT]], ptr [[GEP11]], align 4
422422
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
423423
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
424-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
424+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
425425
; IF-EVL: [[EXIT]]:
426426
; IF-EVL-NEXT: ret void
427427
;
@@ -510,7 +510,7 @@ define void @vp_ctlz(ptr %a, ptr %b, i64 %N) {
510510
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
511511
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
512512
; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
513-
; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
513+
; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
514514
; IF-EVL: [[MIDDLE_BLOCK]]:
515515
; IF-EVL-NEXT: br label %[[EXIT:.*]]
516516
; IF-EVL: [[SCALAR_PH]]:
@@ -525,7 +525,7 @@ define void @vp_ctlz(ptr %a, ptr %b, i64 %N) {
525525
; IF-EVL-NEXT: store i32 [[TMP19]], ptr [[GEP3]], align 4
526526
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
527527
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
528-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
528+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
529529
; IF-EVL: [[EXIT]]:
530530
; IF-EVL-NEXT: ret void
531531
;
@@ -609,7 +609,7 @@ define void @vp_cttz(ptr %a, ptr %b, i64 %N) {
609609
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP20]], [[EVL_BASED_IV]]
610610
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP12]]
611611
; IF-EVL-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
612-
; IF-EVL-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
612+
; IF-EVL-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
613613
; IF-EVL: [[MIDDLE_BLOCK]]:
614614
; IF-EVL-NEXT: br label %[[EXIT:.*]]
615615
; IF-EVL: [[SCALAR_PH]]:
@@ -624,7 +624,7 @@ define void @vp_cttz(ptr %a, ptr %b, i64 %N) {
624624
; IF-EVL-NEXT: store i32 [[TMP23]], ptr [[GEP3]], align 4
625625
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
626626
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
627-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
627+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
628628
; IF-EVL: [[EXIT]]:
629629
; IF-EVL-NEXT: ret void
630630
;
@@ -711,7 +711,7 @@ define void @vp_lrint(ptr %a, ptr %b, i64 %N) {
711711
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
712712
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
713713
; IF-EVL-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
714-
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
714+
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
715715
; IF-EVL: [[MIDDLE_BLOCK]]:
716716
; IF-EVL-NEXT: br label %[[EXIT:.*]]
717717
; IF-EVL: [[SCALAR_PH]]:
@@ -728,7 +728,7 @@ define void @vp_lrint(ptr %a, ptr %b, i64 %N) {
728728
; IF-EVL-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 4
729729
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
730730
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
731-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
731+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
732732
; IF-EVL: [[EXIT]]:
733733
; IF-EVL-NEXT: ret void
734734
;
@@ -819,7 +819,7 @@ define void @vp_llrint(ptr %a, ptr %b, i64 %N) {
819819
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
820820
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
821821
; IF-EVL-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
822-
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
822+
; IF-EVL-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
823823
; IF-EVL: [[MIDDLE_BLOCK]]:
824824
; IF-EVL-NEXT: br label %[[EXIT:.*]]
825825
; IF-EVL: [[SCALAR_PH]]:
@@ -836,7 +836,7 @@ define void @vp_llrint(ptr %a, ptr %b, i64 %N) {
836836
; IF-EVL-NEXT: store i32 [[CONV3]], ptr [[GEP5]], align 4
837837
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
838838
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
839-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
839+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]]
840840
; IF-EVL: [[EXIT]]:
841841
; IF-EVL-NEXT: ret void
842842
;
@@ -925,7 +925,7 @@ define void @vp_abs(ptr %a, ptr %b, i64 %N) {
925925
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
926926
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
927927
; IF-EVL-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
928-
; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
928+
; IF-EVL-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
929929
; IF-EVL: [[MIDDLE_BLOCK]]:
930930
; IF-EVL-NEXT: br label %[[EXIT:.*]]
931931
; IF-EVL: [[SCALAR_PH]]:
@@ -940,7 +940,7 @@ define void @vp_abs(ptr %a, ptr %b, i64 %N) {
940940
; IF-EVL-NEXT: store i32 [[COND]], ptr [[GEP9]], align 4
941941
; IF-EVL-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
942942
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
943-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]
943+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP20:![0-9]+]]
944944
; IF-EVL: [[EXIT]]:
945945
; IF-EVL-NEXT: ret void
946946
;
@@ -1046,24 +1046,25 @@ declare i64 @llvm.lrint.i64.f64(double)
10461046
declare i64 @llvm.llrint.i64.f64(double)
10471047
declare i32 @llvm.abs.i32(i32, i1 immarg)
10481048
;.
1049-
; IF-EVL: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
1049+
; IF-EVL: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
10501050
; IF-EVL: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
1051-
; IF-EVL: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
1052-
; IF-EVL: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
1053-
; IF-EVL: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
1054-
; IF-EVL: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
1055-
; IF-EVL: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
1056-
; IF-EVL: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}
1057-
; IF-EVL: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
1058-
; IF-EVL: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}
1059-
; IF-EVL: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
1060-
; IF-EVL: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}
1061-
; IF-EVL: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}
1062-
; IF-EVL: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]}
1063-
; IF-EVL: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]}
1064-
; IF-EVL: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]]}
1065-
; IF-EVL: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}
1066-
; IF-EVL: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]}
1067-
; IF-EVL: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]}
1068-
; IF-EVL: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]]}
1051+
; IF-EVL: [[META2]] = !{!"llvm.loop.isvectorized.tailfoldingstyle", !"evl"}
1052+
; IF-EVL: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
1053+
; IF-EVL: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]]}
1054+
; IF-EVL: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]], [[META3]]}
1055+
; IF-EVL: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]]}
1056+
; IF-EVL: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]], [[META3]]}
1057+
; IF-EVL: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]]}
1058+
; IF-EVL: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]], [[META3]]}
1059+
; IF-EVL: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]}
1060+
; IF-EVL: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]], [[META3]]}
1061+
; IF-EVL: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]]}
1062+
; IF-EVL: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]], [[META2]], [[META3]]}
1063+
; IF-EVL: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]]}
1064+
; IF-EVL: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]], [[META2]], [[META3]]}
1065+
; IF-EVL: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]]}
1066+
; IF-EVL: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]], [[META2]], [[META3]]}
1067+
; IF-EVL: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]]}
1068+
; IF-EVL: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]], [[META2]], [[META3]]}
1069+
; IF-EVL: [[LOOP20]] = distinct !{[[LOOP20]], [[META1]]}
10691070
;.

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