Is there a way to fix the syntax highliting for vlang? #13527
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Hi, As you can see in the screenshot below, the syntax highlighting seems a bit broken: I believe this might be a Tree-sitter issue—though I'm not 100% sure. Is the Tree-sitter grammar for vlang integrated directly into the Helix repo? If so, is there a way to modify or patch it just for V? Sorry if this is a weird question—I'm a bit confused on how to approach fixing it. If someone can point me in the right direction, I’m happy to try fixing it myself. (Also its not a theme issue it does that with every theme) Thanks! |
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I think the issue here is both Verilog and V using the same file extension. You can use |
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oh yea its verilog. i found #6164 , to fix it i added this to my languages.toml
Thanks!