write V with helix #2837
Answered
by
the-mikedavis
cooperspencer
asked this question in
Q&A
-
Hi, Can anyone help me out? |
Beta Was this translation helpful? Give feedback.
Answered by
the-mikedavis
Jun 20, 2022
Replies: 1 comment 3 replies
-
V and Verilog clash because they both use the |
Beta Was this translation helpful? Give feedback.
3 replies
Answer selected by
cooperspencer
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
V and Verilog clash because they both use the
.v
extension for files. To force V, you can remove thev
extension from Verilog's configuration: #2526 (comment)