prepare wasm support for aarch64 and riscv64

Author: stlankes

Cargo.toml

@@ -171,18 +171,26 @@ free-list = { version = "0.3", features = ["x86_64"] }
 raw-cpuid = "11"
 uart_16550 = "0.4"
 x86_64 = "0.15"
+<<<<<<< HEAD
 memory_addresses = { version = "0.2.3", default-features = false, features = [
 	"x86_64",
 	"conv-x86_64",
 ] }
+=======
+wasmtime = { version = "22.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }
+>>>>>>> cd1d8b6fa (prepare wasm support for aarch64 and riscv64)
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64 = { version = "0.0.14", default-features = false }
 arm-gic = { version = "0.6" }
 semihosting = { version = "0.1", optional = true }
+<<<<<<< HEAD
 memory_addresses = { version = "0.2.3", default-features = false, features = [
 	"aarch64",
 ] }
+=======
+wasmtime = { version = "22.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }
+>>>>>>> cd1d8b6fa (prepare wasm support for aarch64 and riscv64)
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 riscv = "0.14"

src/arch/aarch64/kernel/longjmp.s

@@ -0,0 +1,18 @@
+# The code is derived from the musl implementation
+# of longjmp.
+.section .text
+.global longjmp
+longjmp:
+	# IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
+	ldp x19, x20, [x0,#0]
+	ldp x21, x22, [x0,#16]
+	ldp x23, x24, [x0,#32]
+	ldp x25, x26, [x0,#48]
+	ldp x27, x28, [x0,#64]
+	ldp x29, x30, [x0,#80]
+	ldr x2, [x0,#104]
+	mov sp, x2
+
+	cmp w1, 0
+	csinc w0, w1, wzr, ne
+	br x30

src/arch/aarch64/kernel/mod.rs

@@ -31,6 +31,55 @@ use crate::arch::aarch64::mm::paging::{BasePageSize, PageSize};
 use crate::config::*;
 use crate::env;
 
+const SERIAL_PORT_BAUDRATE: u32 = 115_200;
+
+global_asm!(include_str!("setjmp.s"));
+global_asm!(include_str!("longjmp.s"));
+
+pub(crate) struct Console {
+	serial_port: SerialPort,
+}
+
+impl Console {
+	pub fn new() -> Self {
+		CoreLocal::install();
+
+		let base = env::boot_info()
+			.hardware_info
+			.serial_port_base
+			.map(|uartport| uartport.get())
+			.unwrap_or_default()
+			.try_into()
+			.unwrap();
+
+		let serial_port = SerialPort::new(base);
+
+		serial_port.init(SERIAL_PORT_BAUDRATE);
+
+		Self { serial_port }
+	}
+
+	pub fn write(&mut self, buf: &[u8]) {
+		self.serial_port.write_buf(buf);
+	}
+
+	pub fn read(&mut self) -> Option<u8> {
+		None
+	}
+
+	pub fn is_empty(&self) -> bool {
+		true
+	}
+
+	pub fn register_waker(&mut self, _waker: &Waker) {}
+}
+
+impl Default for Console {
+	fn default() -> Self {
+		Self::new()
+	}
+}
+
 #[repr(align(8))]
 pub(crate) struct AlignedAtomicU32(AtomicU32);
 

src/arch/aarch64/kernel/setjmp.s

@@ -0,0 +1,16 @@
+# The code is derived from the musl implementation
+# of setjmp.
+.section .text
+.global setjmp
+setjmp:
+    # IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
+	stp x19, x20, [x0,#0]
+	stp x21, x22, [x0,#16]
+	stp x23, x24, [x0,#32]
+	stp x25, x26, [x0,#48]
+	stp x27, x28, [x0,#64]
+	stp x29, x30, [x0,#80]
+	mov x2, sp
+	str x2, [x0,#104]
+	mov x0, #0
+	ret

src/arch/riscv64/kernel/longjmp.s

@@ -0,0 +1,23 @@
+# The code is derived from the musl implementation
+# of longjmp.
+.section .text
+.global longjmp
+longjmp:
+    ld s0,    0(a0)
+	ld s1,    8(a0)
+	ld s2,    16(a0)
+	ld s3,    24(a0)
+	ld s4,    32(a0)
+	ld s5,    40(a0)
+	ld s6,    48(a0)
+	ld s7,    56(a0)
+	ld s8,    64(a0)
+	ld s9,    72(a0)
+	ld s10,   80(a0)
+	ld s11,   88(a0)
+	ld sp,    96(a0)
+	ld ra,    104(a0)
+
+	seqz a0, a1
+	add a0, a0, a1
+	ret

src/arch/riscv64/kernel/mod.rs

@@ -19,6 +19,7 @@ mod start;
 pub mod switch;
 pub mod systemtime;
 use alloc::vec::Vec;
+use core::arch::global_asm;
 use core::ptr;
 use core::sync::atomic::{AtomicPtr, AtomicU32, AtomicU64, Ordering};
 
@@ -35,6 +36,41 @@ use crate::env;
 use crate::init_cell::InitCell;
 use crate::mm::physicalmem::PHYSICAL_FREE_LIST;
 
+pub(crate) struct Console {}
+
+impl Console {
+	pub fn new() -> Self {
+		CoreLocal::install();
+
+		Self {}
+	}
+
+	pub fn write(&mut self, buf: &[u8]) {
+		for byte in buf {
+			sbi_rt::console_write_byte(*byte);
+		}
+	}
+
+	pub fn read(&mut self) -> Option<u8> {
+		None
+	}
+
+	pub fn is_empty(&self) -> bool {
+		true
+	}
+
+	pub fn register_waker(&mut self, _waker: &Waker) {}
+}
+
+impl Default for Console {
+	fn default() -> Self {
+		Self::new()
+	}
+}
+
+global_asm!(include_str!("setjmp.s"));
+global_asm!(include_str!("longjmp.s"));
+
 // Used to store information about available harts. The index of the hart in the vector
 // represents its CpuId and does not need to match its hart_id
 pub(crate) static HARTS_AVAILABLE: InitCell<Vec<usize>> = InitCell::new(Vec::new());

src/arch/riscv64/kernel/setjmp.s

@@ -0,0 +1,22 @@
+# The code is derived from the musl implementation
+# of setjmp.
+.section .text
+.global setjmp
+setjmp:
+	sd s0,    0(a0)
+	sd s1,    8(a0)
+	sd s2,    16(a0)
+	sd s3,    24(a0)
+	sd s4,    32(a0)
+	sd s5,    40(a0)
+	sd s6,    48(a0)
+	sd s7,    56(a0)
+	sd s8,    64(a0)
+	sd s9,    72(a0)
+	sd s10,   80(a0)
+	sd s11,   88(a0)
+	sd sp,    96(a0)
+	sd ra,    104(a0)
+
+	li a0, 0
+	ret

src/lib.rs

@@ -82,7 +82,7 @@ mod shell;
 mod synch;
 pub mod syscalls;
 pub mod time;
-#[cfg(all(target_arch = "x86_64", feature = "wasm"))]
+#[cfg(all(any(target_arch = "x86_64", target_arch = "aarch64"), feature = "wasm"))]
 mod wasm;
 
 mod built_info {
@@ -149,7 +149,7 @@ extern "C" fn initd(_arg: usize) {
 	#[cfg(not(test))]
 	let (argc, argv, environ) = syscalls::get_application_parameters();
 
-	#[cfg(all(target_arch = "x86_64", feature = "wasm"))]
+	#[cfg(all(any(target_arch = "x86_64", target_arch = "aarch64"), feature = "wasm"))]
 	if crate::wasm::init().is_err() {
 		error!("Unable to initialized wasm support")
 	}