style: remove mixed whitespaces

Author: mkroening

src/arch/aarch64/kernel/pci.rs

@@ -175,7 +175,7 @@ fn detect_interrupt(
 		// The 3rd cell is the flags, encoded as follows:
 		// bits[3:0] trigger type and level flags.
 		//		1 = low-to-high edge triggered
-		// 		2 = high-to-low edge triggered (invalid for SPIs)
+		//		2 = high-to-low edge triggered (invalid for SPIs)
 		//		4 = active high level-sensitive
 		//		8 = active low level-sensitive (invalid for SPIs).
 		// bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of

src/arch/aarch64/kernel/scheduler.rs

@@ -303,10 +303,8 @@ impl TaskFrame for Task {
 				(*state).tpidr_el0 = tls.thread_ptr().expose_provenance() as u64;
 			}
 
-			/*
-			 * The elr_el1 needs to hold the address of the
-			 * first function to be called when returning from exception handler.
-			 */
+			// The elr_el1 needs to hold the address of the
+			// first function to be called when returning from exception handler.
 			(*state).elr_el1 = task_start;
 			(*state).x0 = func as usize as u64; // use second argument to transfer the entry point
 			(*state).x1 = arg as u64;

src/arch/aarch64/kernel/start.s

@@ -281,9 +281,9 @@ el1_error_invalid:
 .global vector_table
 vector_table:
 /* Current EL with SP0 */
-ventry el1_sp0_sync  	        // Synchronous EL1t
-ventry el1_sp0_irq	        // IRQ EL1t
-ventry el1_sp0_fiq   	        // FIQ EL1t
+ventry el1_sp0_sync             // Synchronous EL1t
+ventry el1_sp0_irq              // IRQ EL1t
+ventry el1_sp0_fiq              // FIQ EL1t
 ventry el1_sp0_error            // Error EL1t
 
 /* Current EL with SPx */

src/arch/riscv64/mm/paging.rs

@@ -417,12 +417,6 @@ where
 	) {
 		assert!(L::LEVEL >= S::MAP_LEVEL);
 
-		// trace!(
-		// 	"Mapping frame {:#X} to page {:#X}",
-		// 	physical_address,
-		// 	page.virtual_address,
-		// );
-
 		if L::LEVEL > S::MAP_LEVEL {
 			let index = page.table_index::<L>();
 
@@ -567,11 +561,6 @@ pub fn virtual_to_physical(virtual_address: VirtAddr) -> Option<PhysAddr> {
 			}
 			let ppn = pte.address().as_u64();
 			for j in i..PAGE_LEVELS {
-				// trace!(
-				// 	"ppn: {:#X}, {:#X}",
-				// 	ppn,
-				// 	ppn & (PAGE_MAP_MASK << (PAGE_BITS + j * PAGE_MAP_BITS)) as u64
-				// );
 				phys_address |= ppn & (PAGE_MAP_MASK << (PAGE_BITS + j * PAGE_MAP_BITS)) as u64;
 			}
 			return Some(PhysAddr::new(phys_address));

src/drivers/net/gem.rs

@@ -84,7 +84,7 @@ register_bitfields! [
 			DBW64 = 1,
 			DBW128 = 2
 		],
-		MDCCLKDIV 	OFFSET(18) NUMBITS(3) [
+		MDCCLKDIV	OFFSET(18) NUMBITS(3) [
 			CLK_DIV8 = 0,
 			CLK_DIV16 = 1,
 			CLK_DIV32 = 2,
@@ -659,9 +659,6 @@ pub fn init_device(
 		// Program the Network Control Register
 
 		// Enable MDIO and enable transmitter/receiver
-		// (*gem).network_control.modify(
-		// 	NetworkControl::MDEN::SET + NetworkControl::TXEN::SET + NetworkControl::RXEN::SET,
-		// );
 		(*gem).network_control.modify(NetworkControl::MDEN::SET);
 
 		// PHY Initialization

src/scheduler/task/mod.rs

@@ -708,7 +708,7 @@ impl BlockedTaskQueue {
 
 		let new_task_wakeup_time = self.list.front().and_then(|task| task.wakeup_time);
 		cfg_if::cfg_if! {
-			if 	#[cfg(feature = "net")] {
+			if #[cfg(feature = "net")] {
 				let network_wakeup_time = self.network_wakeup_time;
 			} else {
 				let network_wakeup_time = None;