From 652038849579e315803a1fc7fb8d93e86ac3c0f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Kr=C3=B6ning?= Date: Wed, 8 Oct 2025 12:01:16 +0200 Subject: [PATCH] build(deps): upgrade arm-gic to 0.7 --- Cargo.lock | 4 +- Cargo.toml | 2 +- src/arch/aarch64/kernel/interrupts.rs | 87 ++++++++++++++++----------- src/arch/aarch64/kernel/mmio.rs | 24 +++++--- src/arch/aarch64/kernel/pci.rs | 12 ++-- src/scheduler/mod.rs | 7 ++- 6 files changed, 82 insertions(+), 54 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 146baf6ee9..6ea06f186d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -139,9 +139,9 @@ checksum = "a23eb6b1614318a8071c9b2521f36b424b2c83db5eb3a0fead4a6c0809af6e61" [[package]] name = "arm-gic" -version = "0.6.1" +version = "0.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6bfdb03424c95b58315a4cb0ff4ca919568a5a28ae5ba960a1ad92c9ccaf49b9" +checksum = "fc8a5b06c02f993e98b0b3eb95c3acefb6889cc33a630621fb3e6c564502c2b0" dependencies = [ "bitflags 2.9.4", "safe-mmio", diff --git a/Cargo.toml b/Cargo.toml index ffbc53bc8d..d52be367f2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -177,7 +177,7 @@ memory_addresses = { version = "0.2.3", default-features = false, features = [ [target.'cfg(target_arch = "aarch64")'.dependencies] aarch64 = { version = "0.0.14", default-features = false } -arm-gic = { version = "0.6" } +arm-gic = { version = "0.7" } arm-pl011-uart = { version = "0.3", default-features = false } semihosting = { version = "0.1", optional = true } memory_addresses = { version = "0.2.3", default-features = false, features = [ diff --git a/src/arch/aarch64/kernel/interrupts.rs b/src/arch/aarch64/kernel/interrupts.rs index 7aa8702502..59051671bc 100644 --- a/src/arch/aarch64/kernel/interrupts.rs +++ b/src/arch/aarch64/kernel/interrupts.rs @@ -1,11 +1,13 @@ use alloc::collections::{BTreeMap, VecDeque}; use core::arch::asm; +use core::ptr::NonNull; use core::sync::atomic::{AtomicU64, Ordering}; use aarch64::regs::*; use ahash::RandomState; -use arm_gic::gicv3::{GicV3, InterruptGroup, SgiTarget, SgiTargetGroup}; -use arm_gic::{IntId, Trigger}; +use arm_gic::gicv3::registers::{Gicd, GicrSgi}; +use arm_gic::gicv3::{GicCpuInterface, GicV3, InterruptGroup, SgiTarget, SgiTargetGroup}; +use arm_gic::{IntId, Trigger, UniqueMmioPointer}; use fdt::standard_nodes::Compatible; use free_list::PageLayout; use hashbrown::HashMap; @@ -127,7 +129,7 @@ pub(crate) fn install_handlers() { #[unsafe(no_mangle)] pub(crate) extern "C" fn do_fiq(_state: &State) -> *mut usize { - if let Some(irqid) = GicV3::get_and_acknowledge_interrupt(InterruptGroup::Group1) { + if let Some(irqid) = GicCpuInterface::get_and_acknowledge_interrupt(InterruptGroup::Group1) { let vector: u8 = u32::from(irqid).try_into().unwrap(); debug!("Receive fiq {vector}"); @@ -143,7 +145,7 @@ pub(crate) extern "C" fn do_fiq(_state: &State) -> *mut usize { crate::executor::run(); core_scheduler().handle_waiting_tasks(); - GicV3::end_interrupt(irqid, InterruptGroup::Group1); + GicCpuInterface::end_interrupt(irqid, InterruptGroup::Group1); return core_scheduler().scheduler().unwrap_or_default(); } @@ -153,7 +155,7 @@ pub(crate) extern "C" fn do_fiq(_state: &State) -> *mut usize { #[unsafe(no_mangle)] pub(crate) extern "C" fn do_irq(_state: &State) -> *mut usize { - if let Some(irqid) = GicV3::get_and_acknowledge_interrupt(InterruptGroup::Group1) { + if let Some(irqid) = GicCpuInterface::get_and_acknowledge_interrupt(InterruptGroup::Group1) { let vector: u8 = u32::from(irqid).try_into().unwrap(); debug!("Receive interrupt {vector}"); @@ -169,7 +171,7 @@ pub(crate) extern "C" fn do_irq(_state: &State) -> *mut usize { crate::executor::run(); core_scheduler().handle_waiting_tasks(); - GicV3::end_interrupt(irqid, InterruptGroup::Group1); + GicCpuInterface::end_interrupt(irqid, InterruptGroup::Group1); trace!("Disabling floating point"); @@ -209,8 +211,10 @@ pub(crate) extern "C" fn do_sync(state: &State) { error!("Table Base Register {:#x}", TTBR0_EL1.get()); error!("Exception Syndrome Register {esr:#x}"); - if let Some(irqid) = GicV3::get_and_acknowledge_interrupt(InterruptGroup::Group1) { - GicV3::end_interrupt(irqid, InterruptGroup::Group1); + if let Some(irqid) = + GicCpuInterface::get_and_acknowledge_interrupt(InterruptGroup::Group1) + { + GicCpuInterface::end_interrupt(irqid, InterruptGroup::Group1); } else { error!("Unable to acknowledge interrupt!"); } @@ -263,7 +267,7 @@ pub fn wakeup_core(core_id: CoreId) { debug!("Wakeup core {core_id}"); let reschedid = IntId::sgi(SGI_RESCHED.into()); - GicV3::send_sgi( + GicCpuInterface::send_sgi( reschedid, SgiTarget::List { affinity3: 0, @@ -272,7 +276,8 @@ pub fn wakeup_core(core_id: CoreId) { target_list: 1 << core_id, }, SgiTargetGroup::CurrentGroup1, - ); + ) + .unwrap(); } pub(crate) fn init() { @@ -337,16 +342,12 @@ pub(crate) fn init() { flags, ); - let mut gic = unsafe { - GicV3::new( - gicd_address.as_mut_ptr(), - gicr_address.as_mut_ptr(), - num_cpus, - is_gic_v4, - ) - }; + let gicd = NonNull::new(gicd_address.as_mut_ptr::()).unwrap(); + let gicd = unsafe { UniqueMmioPointer::new(gicd) }; + let gicr_base = NonNull::new(gicr_address.as_mut_ptr::()).unwrap(); + let mut gic = unsafe { GicV3::new(gicd, gicr_base, num_cpus, is_gic_v4) }; gic.setup(cpu_id); - GicV3::set_priority_mask(0xff); + GicCpuInterface::set_priority_mask(0xff); if let Some(timer_node) = fdt.find_compatible(&["arm,armv8-timer", "arm,armv7-timer"]) { let irq_slice = timer_node.property("interrupts").unwrap().value; @@ -380,15 +381,19 @@ pub(crate) fn init() { } else { panic!("Invalid interrupt type"); }; - gic.set_interrupt_priority(timer_irqid, Some(cpu_id), 0x00); + gic.set_interrupt_priority(timer_irqid, Some(cpu_id), 0x00) + .unwrap(); if (irqflags & 0xf) == 4 || (irqflags & 0xf) == 8 { - gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Level); + gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Level) + .unwrap(); } else if (irqflags & 0xf) == 2 || (irqflags & 0xf) == 1 { - gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Edge); + gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Edge) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(timer_irqid, Some(cpu_id), true); + gic.enable_interrupt(timer_irqid, Some(cpu_id), true) + .unwrap(); } if let Some(uart_node) = fdt.find_compatible(&["arm,pl011"]) { @@ -418,20 +423,25 @@ pub(crate) fn init() { } else { panic!("Invalid interrupt type"); }; - gic.set_interrupt_priority(uart_irqid, Some(cpu_id), 0x00); + gic.set_interrupt_priority(uart_irqid, Some(cpu_id), 0x00) + .unwrap(); if (irqflags & 0xf) == 4 || (irqflags & 0xf) == 8 { - gic.set_trigger(uart_irqid, Some(cpu_id), Trigger::Level); + gic.set_trigger(uart_irqid, Some(cpu_id), Trigger::Level) + .unwrap(); } else if (irqflags & 0xf) == 2 || (irqflags & 0xf) == 1 { - gic.set_trigger(uart_irqid, Some(cpu_id), Trigger::Edge); + gic.set_trigger(uart_irqid, Some(cpu_id), Trigger::Edge) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(uart_irqid, Some(cpu_id), true); + gic.enable_interrupt(uart_irqid, Some(cpu_id), true) + .unwrap(); } let reschedid = IntId::sgi(SGI_RESCHED.into()); - gic.set_interrupt_priority(reschedid, Some(cpu_id), 0x01); - gic.enable_interrupt(reschedid, Some(cpu_id), true); + gic.set_interrupt_priority(reschedid, Some(cpu_id), 0x01) + .unwrap(); + gic.enable_interrupt(reschedid, Some(cpu_id), true).unwrap(); IRQ_NAMES.lock().insert(SGI_RESCHED, "Reschedule"); *GIC.lock() = Some(gic); @@ -445,7 +455,7 @@ pub fn init_cpu() { debug!("Mark cpu {cpu_id} as awake"); gic.setup(cpu_id); - GicV3::set_priority_mask(0xff); + GicCpuInterface::set_priority_mask(0xff); let fdt = env::fdt().unwrap(); @@ -471,20 +481,25 @@ pub fn init_cpu() { } else { panic!("Invalid interrupt type"); }; - gic.set_interrupt_priority(timer_irqid, Some(cpu_id), 0x00); + gic.set_interrupt_priority(timer_irqid, Some(cpu_id), 0x00) + .unwrap(); if (irqflags & 0xf) == 4 || (irqflags & 0xf) == 8 { - gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Level); + gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Level) + .unwrap(); } else if (irqflags & 0xf) == 2 || (irqflags & 0xf) == 1 { - gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Edge); + gic.set_trigger(timer_irqid, Some(cpu_id), Trigger::Edge) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(timer_irqid, Some(cpu_id), true); + gic.enable_interrupt(timer_irqid, Some(cpu_id), true) + .unwrap(); } let reschedid = IntId::sgi(SGI_RESCHED.into()); - gic.set_interrupt_priority(reschedid, Some(cpu_id), 0x01); - gic.enable_interrupt(reschedid, Some(cpu_id), true); + gic.set_interrupt_priority(reschedid, Some(cpu_id), 0x01) + .unwrap(); + gic.enable_interrupt(reschedid, Some(cpu_id), true).unwrap(); } } diff --git a/src/arch/aarch64/kernel/mmio.rs b/src/arch/aarch64/kernel/mmio.rs index c50041bf33..0896ce2f4b 100644 --- a/src/arch/aarch64/kernel/mmio.rs +++ b/src/arch/aarch64/kernel/mmio.rs @@ -140,23 +140,27 @@ pub fn init_drivers() { virtio_irqid, Some(cpu_id), 0x00, - ); + ) + .unwrap(); if (irqflags & 0xf) == 4 || (irqflags & 0xf) == 8 { gic.set_trigger( virtio_irqid, Some(cpu_id), Trigger::Level, - ); + ) + .unwrap(); } else if (irqflags & 0xf) == 2 || (irqflags & 0xf) == 1 { gic.set_trigger( virtio_irqid, Some(cpu_id), Trigger::Edge, - ); + ) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(virtio_irqid, Some(cpu_id), true); + gic.enable_interrupt(virtio_irqid, Some(cpu_id), true) + .unwrap(); *NETWORK_DEVICE.lock() = Some(drv); } @@ -182,24 +186,28 @@ pub fn init_drivers() { virtio_irqid, Some(cpu_id), 0x00, - ); + ) + .unwrap(); if (irqflags & 0xf) == 4 || (irqflags & 0xf) == 8 { gic.set_trigger( virtio_irqid, Some(cpu_id), Trigger::Level, - ); + ) + .unwrap(); } else if (irqflags & 0xf) == 2 || (irqflags & 0xf) == 1 { gic.set_trigger( virtio_irqid, Some(cpu_id), Trigger::Edge, - ); + ) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(virtio_irqid, Some(cpu_id), true); + gic.enable_interrupt(virtio_irqid, Some(cpu_id), true) + .unwrap(); register_driver(MmioDriver::VirtioConsole( hermit_sync::InterruptTicketMutex::new(*drv), diff --git a/src/arch/aarch64/kernel/pci.rs b/src/arch/aarch64/kernel/pci.rs index c5a368ca0f..11f5aea2d0 100644 --- a/src/arch/aarch64/kernel/pci.rs +++ b/src/arch/aarch64/kernel/pci.rs @@ -198,15 +198,19 @@ fn detect_interrupt( let mut gic = GIC.lock(); let gic = gic.as_mut().unwrap(); let cpu_id = core_id(); - gic.set_interrupt_priority(irq_id, Some(cpu_id as usize), 0x10); + gic.set_interrupt_priority(irq_id, Some(cpu_id as usize), 0x10) + .unwrap(); if irq_flags == 4 { - gic.set_trigger(irq_id, Some(cpu_id as usize), Trigger::Level); + gic.set_trigger(irq_id, Some(cpu_id as usize), Trigger::Level) + .unwrap(); } else if irq_flags == 2 { - gic.set_trigger(irq_id, Some(cpu_id as usize), Trigger::Edge); + gic.set_trigger(irq_id, Some(cpu_id as usize), Trigger::Edge) + .unwrap(); } else { panic!("Invalid interrupt level!"); } - gic.enable_interrupt(irq_id, Some(cpu_id as usize), true); + gic.enable_interrupt(irq_id, Some(cpu_id as usize), true) + .unwrap(); return Some((pin, irq_number.try_into().unwrap())); } diff --git a/src/scheduler/mod.rs b/src/scheduler/mod.rs index 21f2fb5da1..810b787c51 100644 --- a/src/scheduler/mod.rs +++ b/src/scheduler/mod.rs @@ -139,7 +139,7 @@ impl PerCoreSchedulerExt for &mut PerCoreScheduler { use core::arch::asm; use arm_gic::IntId; - use arm_gic::gicv3::{GicV3, SgiTarget, SgiTargetGroup}; + use arm_gic::gicv3::{GicCpuInterface, SgiTarget, SgiTargetGroup}; use crate::interrupts::SGI_RESCHED; @@ -153,7 +153,7 @@ impl PerCoreSchedulerExt for &mut PerCoreScheduler { #[cfg(not(feature = "smp"))] let core_id = 0; - GicV3::send_sgi( + GicCpuInterface::send_sgi( reschedid, SgiTarget::List { affinity3: 0, @@ -162,7 +162,8 @@ impl PerCoreSchedulerExt for &mut PerCoreScheduler { target_list: 1 << core_id, }, SgiTargetGroup::CurrentGroup1, - ); + ) + .unwrap(); interrupts::enable(); }