Generate HDL code for a given topology

## Description 

Similarly to #14, generating HDL code (such as VHDL or Verilog) allows optimized LTI systems to be deployed to an FPGA or to be manufactured in an ASIC. Having support for HDL generation would be great.

## Definition of done

TBD -- but if #14 is in place, we might be able to use [bambu](https://github.com/ferrandi/PandA-bambu) to generate Verilog from that C code.