D-latch component that can have default value

[jnoche]

In an earlier issue (#334), you mentioned that at the simulation start phase, gates have different, random propagation times. That is why, say, the D latch (level-triggered) in the examples\sequential folder (D.dig) would start at a random state. The solution you proposed was to use memory elements with reset inputs.

Right now, there is a ready-made component called D-Flip-flop (edge-triggered) and its default value can be set (by changing its component properties) without having a reset input.

Is it possible to create a new component called, say, D-Latch (level-triggered) that acts like the D.dig circuit but whose default value can be set (by changing its component properties) without having a reset input?

[hneemann]

Yes.

But to set the default value to 1 you have to add the reset component to the nor gate at the bottom.
Used as a embedded circuit it has only the inputs D and C.

If you want to adjust the default value via the embedding circuit, a generic circuit must be created, which is possible but not easy to understand and therefore may not be suitable for teaching:

D.zip

[jnoche]

(The info I gave above is what Digital shows me when I select Help>About. My OS is actually Windows 11.)

[hneemann]

Please download the update D.zip and try again.

[jnoche]

The new D.dig opens, but the lower NOR gate has only two inputs. I'm changing it to 3 inputs.

[jnoche]

Thank you. I haven't tested it fully, but it seems to be working now.

[hneemann]

The new D.dig opens, but the lower NOR gate has only two inputs. I'm changing it to 3 inputs.

Damn! Today is really not my best day! 😄