"No Verilog code for Delay available" error message on Verilog export

[lynchaj]

Hi
I am getting an error on exporting a Digital circuit to Verilog that I do not understand. Would someone please tell me what I am doing wrong?

This is the circuit I designed. It seems to work in the Analysis function and I can export it to CUPL and/or JEDEC

However, when I try to export to Verilog I get the error message below. Very similar for VHDL export

Thank you in advance for any help. Most appreciated! Thanks! Andrew Lynch

PS, if I delete the 74138 section the error message goes away but I haven't been able to isolate the specific problem. It seems to have something to do with it though

[mengstr]

Open up (right click and "Open Circuit") the 74138 and replace the delay element in it with a plain OR gate (to get the same 1-gate delay) and it should work just fine to export to Verilog.
At least it worked for me a year or two ago doing that. :-)

[lynchaj]

Thank You! Much appreciated.

However, I noticed that the circuit cleaves nicely into two GAL16V8 sized pieces. It actually reduces pin count by 4 and no JTAG port. Plus GAL16V8s are cheap and plentiful. But I do appreciate your answer and may need it again sometime soon.

Thanks again, Andrew Lynch

[lynchaj]

Hi,
Since Digital can't export designs using the 74138 due to the presence of the delay element, is this considered a bug in Digital or a feature?

Especially since the problem can be solved by replacing the delay element with an AND gate, it seems like a bug to me.

Thanks, Andrew Lynch

[hneemann]

Exporting a delay to an HDL like Verilog doesn't make much sense.
If a design is really dependent on where delays are present and where they are not, it probably won't work in an FPGA.
This is because in an FPGA the logic is highly optimized and usually distributed over several CLBs (Configurable Logic Block).
The CLBs can also be cascaded. The timing in the circuit is often not preserved.
Therefore, in a circuit that should work in an FPGA, the timing should only depend on the clock and never on gate propagation times. Hence this error message: If the delay is really necessary, the circuit will most likely not work in an FPGA.
Even if the delay is replaced by an Or gate, this gate is pretty sure to be removed by the analysis tool.
Exporting a delay to Verilog would mean simply omitting it, which is problematic if it is really required.
Therefore it is also not a good idea to design a circuit intended for an FPGA with 74xx chips.
It is much more robust to use only the built-in components, and to make sure that there are no dependencies on gate propagation times or delays.

The delay component in 74138 is used to prevent glitches at the outputs.
If this chip is exported to Verilog, glitches may well occur. Also if the delay gate is replaced by an AND or OR.