[X86] Use MCRegister. NFC

Author: topperc

llvm/lib/Target/X86/AsmParser/X86Operand.h

@@ -628,8 +628,8 @@ struct X86Operand final : public MCParsedAsmOperand {
 
   void addTILEPairOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    unsigned Reg = getReg();
-    switch (Reg) {
+    MCRegister Reg = getReg();
+    switch (Reg.id()) {
     default:
       llvm_unreachable("Invalid tile register!");
     case X86::TMM0:

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

@@ -1181,8 +1181,8 @@ class DarwinX86AsmBackend : public X86AsmBackend {
   unsigned StackDivide;                  ///< Amount to adjust stack size by.
 protected:
   /// Size of a "push" instruction for the given register.
-  unsigned PushInstrSize(unsigned Reg) const {
-    switch (Reg) {
+  unsigned PushInstrSize(MCRegister Reg) const {
+    switch (Reg.id()) {
       case X86::EBX:
       case X86::ECX:
       case X86::EDX:

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -6239,7 +6239,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     }
     if (MI.getOpcode() == X86::AVX512_256_SET0) {
       // No VLX so we must reference a zmm.
-      unsigned ZReg =
+      MCRegister ZReg =
           TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
       MIB->getOperand(0).setReg(ZReg);
     }

llvm/lib/Target/X86/X86MCInstLower.cpp

@@ -444,7 +444,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
     }
     OutMI.setOpcode(NewOpc);
     // Duplicate the destination.
-    unsigned DestReg = OutMI.getOperand(0).getReg();
+    MCRegister DestReg = OutMI.getOperand(0).getReg();
     OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
     break;
   }