[RISCV] Make RISCVInstrInfo::verifyInstruction stricter for immediate-only operands (llvm#170736)

Most of the immediate operands can only be an immediate, but we were
allowing any non-register operand.

Split the immediate-only from the immediate or non-register operands.
The non-register cases could be made even stricter, but I'll leave that
as a TODO.

Author: topperc

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -393,7 +393,6 @@ enum OperandType : unsigned {
   OPERAND_UIMM14_LSB00,
   OPERAND_UIMM16,
   OPERAND_UIMM16_NONZERO,
-  OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_UIMMLOG2XLEN_NONZERO,
   OPERAND_UIMM32,
@@ -412,13 +411,11 @@ enum OperandType : unsigned {
   OPERAND_SIMM10_LSB0000_NONZERO,
   OPERAND_SIMM10_UNSIGNED,
   OPERAND_SIMM11,
-  OPERAND_SIMM12,
   OPERAND_SIMM12_LSB00000,
   OPERAND_SIMM16,
   OPERAND_SIMM16_NONZERO,
   OPERAND_SIMM20_LI,
   OPERAND_SIMM26,
-  OPERAND_BARE_SIMM32,
   OPERAND_CLUI_IMM,
   OPERAND_VTYPEI10,
   OPERAND_VTYPEI11,
@@ -447,6 +444,15 @@ enum OperandType : unsigned {
   // Vtype operand for XSfmm extension.
   OPERAND_XSFMM_VTYPE,
   OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_VTYPE,
+
+  OPERAND_UIMM20_LUI,
+  OPERAND_UIMM20_AUIPC,
+
+  // Simm12 or constant pool, global, basicblock, etc.
+  OPERAND_SIMM12_LO,
+
+  OPERAND_BARE_SIMM32,
+
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.