Questions about how to implement in Sapphire Rapids

[MerlinPendragon]

We are evaluating ultra-fine-grain host-network behaviour on a 2-socket Sapphire Rapids-SP (Intel® Xeon® Gold 6416H) platform.
The current microsec/cha reader rejects the CPU because SPR’s CPUID model (Family 06h, Model 0xB7) is not listed in offsets.json / events.json. As a result, no CHA MSR offsets or event encodings are generated, and cha_reader exits with “unsupported CPU model”.

Adding SPR is valuable because:

1. SPR is now the dominant production SKU for PCIe 5.0 / CXL 1.1 clusters that the repo targets.

2. The new mesh uses 10×9 stop topology, ~32 CHA slices per socket, and several event encodings have changed—critical for reproducing SIGCOMM’24-style µs studies on next-gen hardware.

Could you please give some guidance about how to support SPR? thanks