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refactor: use bitflags-based Extensions for RISC-V decoder CI #61: Pull request #40 synchronize by manchangfengxu
1m 39s manchangfengxu:feat/extension
manchangfengxu:feat/extension
1m 39s
refactor: use bitflags-based Extensions for RISC-V decoder CI #60: Pull request #40 opened by manchangfengxu
3m 11s manchangfengxu:feat/extension
manchangfengxu:feat/extension
3m 11s
feat: add XTheadCondMov RISC-V extension and enable it for RV32GC CI #59: Commit 70efc2a pushed by Plucky923
2m 25s main
main
2m 25s
Add XTheadCondMov RISC-V extension and enable it for RV32GC CI #58: Pull request #39 synchronize by manchangfengxu
1m 41s manchangfengxu:feat/xtheadcondmov
manchangfengxu:feat/xtheadcondmov
1m 41s
Add XTheadCondMov RISC-V extension and enable it for RV32GC CI #57: Pull request #39 synchronize by manchangfengxu
1m 36s manchangfengxu:feat/xtheadcondmov
manchangfengxu:feat/xtheadcondmov
1m 36s
Copilot code review Copilot code review #3: by Copilot AI
3m 18s refs/pull/39/head
refs/pull/39/head
3m 18s
Add XTheadCondMov RISC-V extension and enable it for RV32GC CI #56: Pull request #39 synchronize by manchangfengxu
2m 5s manchangfengxu:feat/xtheadcondmov
manchangfengxu:feat/xtheadcondmov
2m 5s
Add zicsr zicntr CI #55: Pull request #38 synchronize by Daiyuanranfeng
15s Daiyuanranfeng:main
Daiyuanranfeng:main
15s
fix: correct endianness handling in HexParser CI #54: Commit 7ff8b47 pushed by Plucky923
5m 45s main
main
5m 45s
Add XTheadCondMov RISC-V extension and enable it for RV32GC CI #53: Pull request #39 opened by manchangfengxu
2m 8s manchangfengxu:feat/xtheadcondmov
manchangfengxu:feat/xtheadcondmov
2m 8s
Add zicsr zicntr CI #52: Pull request #38 synchronize by Daiyuanranfeng
21s Daiyuanranfeng:main
Daiyuanranfeng:main
21s
Add zicsr zicntr CI #51: Pull request #38 opened by Daiyuanranfeng
13s Daiyuanranfeng:main
Daiyuanranfeng:main
13s
fix: correct endianness handling in HexParser CI #50: Pull request #37 synchronize by lurenjia1213
1m 46s lurenjia1213:main
lurenjia1213:main
1m 46s
fix: correct endianness handling in HexParser CI #48: Pull request #37 synchronize by lurenjia1213
1m 49s lurenjia1213:main
lurenjia1213:main
1m 49s
Copilot code review Copilot code review #2: by Copilot AI
3m 45s refs/pull/37/head
refs/pull/37/head
3m 45s
fix: correct endianness handling in HexParser CI #47: Pull request #37 synchronize by lurenjia1213
1m 33s lurenjia1213:main
lurenjia1213:main
1m 33s
fix: correct endianness handling in HexParser CI #46: Pull request #37 opened by lurenjia1213
1m 41s lurenjia1213:main
lurenjia1213:main
1m 41s
feat: implement RISC-V CSR pseudo-instruction support CI #45: Commit a77f48a pushed by Plucky923
1m 55s main
main
1m 55s
feat: implement RISC-V CSR pseudo-instruction support CI #44: Pull request #33 synchronize by Dayuxiaoshui
2m 58s Dayuxiaoshui:main
Dayuxiaoshui:main
2m 58s
docs: add capstone v6.0.0 feature support list CI #43: Commit 858af2a pushed by Plucky923
2m 0s main
main
2m 0s
Copilot code review Copilot code review #1: by Copilot AI
2m 17s refs/pull/33/head
refs/pull/33/head
2m 17s
docs: add capstone v6.0.0 feature support list CI #42: Pull request #35 synchronize by luojia65
1m 54s rustsbi:docs/capstone-v6.0.0
rustsbi:docs/capstone-v6.0.0
1m 54s
docs: add capstone v6.0.0 feature support list CI #41: Pull request #35 opened by luojia65
2m 17s rustsbi:docs/capstone-v6.0.0
rustsbi:docs/capstone-v6.0.0
2m 17s
feat: implement RISC-V CSR pseudo-instruction support CI #40: Pull request #33 synchronize by Dayuxiaoshui
1m 57s Dayuxiaoshui:main
Dayuxiaoshui:main
1m 57s
feat: implement RISC-V CSR pseudo-instruction support CI #39: Pull request #33 opened by Dayuxiaoshui
13s Dayuxiaoshui:main
Dayuxiaoshui:main
13s