refactor: use bitflags-based Extensions for RISC-V decoder

manchangfengxu · manchangfengxu · commit 08cb4c592c8b · 2025-11-24T20:26:55.000+08:00
- Replace the old u32-based extension_masks with a bitflags::bitflags Extensions type in riscv::extensions
- Update RiscVDecoder, RiscVHandler, and all RISC-V extension is_enabled implementations to use Extensions::contains()
- Keep the existing RiscVExtensions type in riscv::arch for CLI-level configuration unchange

Signed-off-by: manchangfengxu &lt;manchangfengxu@openatom.club&gt;
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/robustone-core/Cargo.toml b/robustone-core/Cargo.toml
@@ -5,6 +5,7 @@ edition = "2024"
 
 [dependencies]
 hex = "0.4"
+bitflags = "2.10.0"
 
 [features]
 default = ["riscv"]
diff --git a/robustone-core/src/riscv/decoder.rs b/robustone-core/src/riscv/decoder.rs
@@ -4,7 +4,7 @@
 //! is implemented as a separate module, making the codebase more maintainable
 //! and easier to extend with new instructions.
 
-use super::extensions::{InstructionExtension, create_extensions, extension_masks};
+use super::extensions::{Extensions, InstructionExtension, create_extensions};
 use super::types::*;
 use crate::error::DisasmError;
 
@@ -19,13 +19,13 @@ pub enum Xlen {
 /// Refactored RISC-V instruction decoder using extension modules.
 pub struct RiscVDecoder {
     xlen: Xlen,
-    extensions: u32,
+    extensions: Extensions,
     extension_handlers: Vec<Box<dyn InstructionExtension>>,
 }
 
 impl RiscVDecoder {
     /// Construct a decoder with the provided XLEN and extension bitmask.
-    pub fn new(xlen: Xlen, extensions: u32) -> Self {
+    pub fn new(xlen: Xlen, extensions: Extensions) -> Self {
         let extension_handlers = create_extensions();
         Self {
             xlen,
@@ -36,28 +36,12 @@ impl RiscVDecoder {
 
     /// Create a decoder with full RV32GC support.
     pub fn rv32gc() -> Self {
-        Self::new(
-            Xlen::X32,
-            extension_masks::I
-                | extension_masks::M
-                | extension_masks::A
-                | extension_masks::F
-                | extension_masks::C
-                | extension_masks::XTHEADCONDMOV,
-        )
+        Self::new(Xlen::X32, Extensions::G | Extensions::C)
     }
 
     /// Create a decoder with full RV64GC support.
     pub fn rv64gc() -> Self {
-        Self::new(
-            Xlen::X64,
-            extension_masks::I
-                | extension_masks::M
-                | extension_masks::A
-                | extension_masks::F
-                | extension_masks::D
-                | extension_masks::C,
-        )
+        Self::new(Xlen::X64, Extensions::G | Extensions::C)
     }
 
     /// Decode a single instruction located at `address`.
@@ -229,7 +213,7 @@ impl RiscVDecoder {
             | ((instruction >> 6) & 0x1) << 6          // imm[6] from instruction[6]
             | ((instruction >> 9) & 0x3) << 7; // imm[8:7] from instruction[9:8]
 
-        if self.extensions & extension_masks::C == 0 {
+        if !self.extensions.contains(Extensions::C) {
             eprintln!("Warning: Decoding compressed instruction while C extension is disabled");
         }
 
@@ -334,20 +318,16 @@ mod tests {
     fn test_refactored_decoder_creation() {
         let decoder = RiscVDecoder::rv32gc();
         assert_eq!(decoder.xlen, Xlen::X32);
-        assert!(decoder.extensions & extension_masks::I != 0);
+        assert!(decoder.extensions.contains(Extensions::I));
 
         let decoder = RiscVDecoder::rv64gc();
         assert_eq!(decoder.xlen, Xlen::X64);
-        assert!(decoder.extensions & extension_masks::I != 0);
+        assert!(decoder.extensions.contains(Extensions::I));
 
         let decoder = RiscVDecoder::rv64gc();
         assert_eq!(decoder.xlen, Xlen::X64);
-        assert!(decoder.extensions & extension_masks::I != 0);
-        assert!(decoder.extensions & extension_masks::M != 0);
-        assert!(decoder.extensions & extension_masks::A != 0);
-        assert!(decoder.extensions & extension_masks::F != 0);
-        assert!(decoder.extensions & extension_masks::D != 0);
-        assert!(decoder.extensions & extension_masks::C != 0);
+        assert!(decoder.extensions.contains(Extensions::G));
+        assert!(decoder.extensions.contains(Extensions::C));
     }
 
     #[test]
diff --git a/robustone-core/src/riscv/extensions/mod.rs b/robustone-core/src/riscv/extensions/mod.rs
@@ -5,6 +5,22 @@
 
 use super::decoder::{RiscVDecodedInstruction, Xlen};
 use crate::error::DisasmError;
+use bitflags::bitflags;
+
+bitflags! {
+    /// Bitflags representing enabled RISC-V extensions.
+    #[derive(Clone, Copy)]
+    pub struct Extensions: u32 {
+        const G             = Self::I.bits() | Self::M.bits() | Self::A.bits() | Self::F.bits() | Self::D.bits();
+        const I             = 1 << 0;
+        const M             = 1 << 1;
+        const A             = 1 << 2;
+        const F             = 1 << 3;
+        const D             = 1 << 4;
+        const C             = 1 << 5;
+        const XTHEADCONDMOV = 1 << 6;
+    }
+}
 
 /// Trait that all instruction set extensions must implement.
 #[allow(clippy::too_many_arguments)]
@@ -65,7 +81,7 @@ pub trait InstructionExtension: Sync {
     fn name(&self) -> &'static str;
 
     /// Check if this extension is enabled for the given configuration.
-    fn is_enabled(&self, extensions: u32) -> bool;
+    fn is_enabled(&self, extensions: Extensions) -> bool;
 }
 
 // Standard RISC-V extension modules
@@ -99,14 +115,3 @@ pub fn create_extensions() -> Vec<Box<dyn InstructionExtension>> {
         Box::new(XTheadCondMovExtension::new()),
     ]
 }
-
-/// Extension bit masks for standard RISC-V and XuanTie extensions.
-pub mod extension_masks {
-    pub const I: u32 = 0b001; // Base Integer Instruction Set
-    pub const M: u32 = 0b010; // Multiply and Divide
-    pub const A: u32 = 0b100; // Atomic Instructions
-    pub const F: u32 = 0b1000; // Single-Precision Floating-Point
-    pub const D: u32 = 0b10000; // Double-Precision Floating-Point
-    pub const C: u32 = 0b100000; // Compressed Instructions
-    pub const XTHEADCONDMOV: u32 = 0b1000000; // XTheadCondMov - Conditional Move
-}
diff --git a/robustone-core/src/riscv/extensions/rva.rs b/robustone-core/src/riscv/extensions/rva.rs
@@ -9,9 +9,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RVA Atomic Instructions Extension
 pub struct RvaExtension {
@@ -116,9 +115,9 @@ impl InstructionExtension for RvaExtension {
         "A"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // A extension bit (bit 2)
-        extensions & extension_masks::A != 0
+        extensions.contains(Extensions::A)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/extensions/rvc.rs b/robustone-core/src/riscv/extensions/rvc.rs
@@ -10,9 +10,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RVC Compressed Instructions Extension
 pub struct RvcExtension {
@@ -371,9 +370,9 @@ impl InstructionExtension for RvcExtension {
         "C"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // C extension bit (bit 5)
-        extensions & extension_masks::C != 0
+        extensions.contains(Extensions::C)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/extensions/rvd.rs b/robustone-core/src/riscv/extensions/rvd.rs
@@ -9,9 +9,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RVD Double-Precision Floating-Point Extension
 pub struct RvdExtension {
@@ -176,9 +175,9 @@ impl InstructionExtension for RvdExtension {
         "D"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // D extension bit (bit 4)
-        extensions & extension_masks::D != 0
+        extensions.contains(Extensions::D)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/extensions/rvf.rs b/robustone-core/src/riscv/extensions/rvf.rs
@@ -9,9 +9,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RVF Single-Precision Floating-Point Extension
 pub struct RvfExtension {
@@ -176,9 +175,9 @@ impl InstructionExtension for RvfExtension {
         "F"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // F extension bit (bit 3)
-        extensions & extension_masks::F != 0
+        extensions.contains(Extensions::F)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/extensions/rvi.rs b/robustone-core/src/riscv/extensions/rvi.rs
@@ -13,9 +13,8 @@ use super::super::shared::{
     registers::RegisterManager,
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RV32I/RV64I Base Integer Extension
 pub struct RviExtension {
@@ -643,9 +642,9 @@ impl InstructionExtension for RviExtension {
         "I"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // I extension is always enabled (bit 0)
-        extensions & extension_masks::I != 0
+        extensions.contains(Extensions::I)
     }
 
     fn try_decode_standard(
@@ -731,8 +730,8 @@ mod tests {
     fn test_rvi_extension_creation() {
         let extension = RviExtension::new();
         assert_eq!(extension.name(), "I");
-        assert!(extension.is_enabled(0b001));
-        assert!(!extension.is_enabled(0b010));
+        assert!(extension.is_enabled(Extensions::I));
+        assert!(!extension.is_enabled(Extensions::M));
     }
 
     #[test]
diff --git a/robustone-core/src/riscv/extensions/rvm.rs b/robustone-core/src/riscv/extensions/rvm.rs
@@ -10,9 +10,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// RVM Multiply and Divide Extension
 pub struct RvmExtension {
@@ -101,9 +100,9 @@ impl InstructionExtension for RvmExtension {
         "M"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // M extension bit (bit 1)
-        extensions & extension_masks::M != 0
+        extensions.contains(Extensions::M)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/extensions/xtheadcondmov.rs b/robustone-core/src/riscv/extensions/xtheadcondmov.rs
@@ -10,9 +10,8 @@ use super::super::shared::{
     registers::{RegisterManager, RegisterNameProvider},
 };
 use super::super::types::*;
-use super::InstructionExtension;
+use super::{Extensions, InstructionExtension};
 use crate::error::DisasmError;
-use crate::riscv::extensions::extension_masks;
 
 /// XTheadCondMov Conditional Move Extension
 pub struct XTheadCondMovExtension {
@@ -68,9 +67,9 @@ impl InstructionExtension for XTheadCondMovExtension {
         "XTheadCondMov"
     }
 
-    fn is_enabled(&self, extensions: u32) -> bool {
+    fn is_enabled(&self, extensions: Extensions) -> bool {
         // XTheadCondMov extension bit
-        extensions & extension_masks::XTHEADCONDMOV != 0
+        extensions.contains(Extensions::XTHEADCONDMOV)
     }
 
     fn try_decode_standard(
diff --git a/robustone-core/src/riscv/mod.rs b/robustone-core/src/riscv/mod.rs
@@ -19,6 +19,7 @@ pub mod types;
 use crate::{ArchitectureHandler, error::DisasmError, instruction::Instruction};
 use arch::RiscVInstructionDetail;
 use decoder::{RiscVDecoder, Xlen};
+use extensions::Extensions;
 use types::*;
 
 /// Architecture handler implementation for RISC-V targets.
@@ -50,7 +51,7 @@ impl RiscVHandler {
     }
 
     /// Creates a handler with custom XLEN and extension flags.
-    pub fn with_extensions(xlen: Xlen, extensions: u32) -> Self {
+    pub fn with_extensions(xlen: Xlen, extensions: Extensions) -> Self {
         Self {
             decoder: RiscVDecoder::new(xlen, extensions),
         }
