refactor(core)!: return register usage by reference to avoid clones

Change InstructionDetail::registers_read and registers_written return type from Vec to &[u32].
Update implementations:
	BasicInstructionDetail now returns &self.regs_read / &self.regs_write.
	RiscVInstructionDetail now returns &self.regs_read / &self.regs_write.

Signed-off-by: manchangfengxu <manchangfengxu@openatom.club>

Author: manchangfengxu

robustone-core/src/instruction.rs

@@ -261,10 +261,10 @@ pub trait InstructionDetail: std::fmt::Debug + Send + Sync {
     fn architecture_name(&self) -> &'static str;
 
     /// Returns a list of register identifiers that are read by this instruction.
-    fn registers_read(&self) -> Vec<u32>;
+    fn registers_read(&self) -> &[u32];
 
     /// Returns a list of register identifiers that are written by this instruction.
-    fn registers_written(&self) -> Vec<u32>;
+    fn registers_written(&self) -> &[u32];
 }
 
 /// A generic implementation of `InstructionDetail` for simple use cases.
@@ -335,12 +335,12 @@ impl InstructionDetail for BasicInstructionDetail {
         self.architecture
     }
 
-    fn registers_read(&self) -> Vec<u32> {
-        self.regs_read.clone()
+    fn registers_read(&self) -> &[u32] {
+        &self.regs_read
     }
 
-    fn registers_written(&self) -> Vec<u32> {
-        self.regs_write.clone()
+    fn registers_written(&self) -> &[u32] {
+        &self.regs_write
     }
 }
 

robustone-core/src/riscv/arch.rs

@@ -157,12 +157,12 @@ impl crate::instruction::InstructionDetail for RiscVInstructionDetail {
         "riscv"
     }
 
-    fn registers_read(&self) -> Vec<u32> {
-        self.regs_read.clone()
+    fn registers_read(&self) -> &[u32] {
+        &self.regs_read
     }
 
-    fn registers_written(&self) -> Vec<u32> {
-        self.regs_write.clone()
+    fn registers_written(&self) -> &[u32] {
+        &self.regs_write
     }
 }