Implement RISC-V RVA23 Supervisor extensions: Svbare, Sstvecd, Sstvala, Sscounterenw

[luojia65]

Those extensions should be supported. According to RVA23 profile (here):

• Svbare, Sv39: Bare mode virtual-memory translation supported

Supports CSR satp in Robustone.

• Sstvecd: stvec supports Direct mode

stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

Supports CSR stvec in Robustone.

• Sstvala: stval provides all needed values

stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the ebreak or c.ebreak instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.

Supports CSR stval in Robustone.

• Sscounterenw: Support writeable enables for any supported counter

For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

Supports CSR scounteren in Robustone.