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Added a new regression
Signed-off-by: Jaehyun Kim <[email protected]>
1 parent 8236e85 commit a89a1c7

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‎src/odb/test/BUILD‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,7 @@ COMPULSORY_TESTS = [
189189
"replace_hier_mod3",
190190
"replace_hier_mod4",
191191
"replace_hier_mod5",
192+
"replace_hier_mod6",
192193
"replace_hier_mod_report_checks",
193194
"rounding",
194195
"row_settings",
@@ -306,6 +307,7 @@ filegroup(
306307
"helper.tcl",
307308
"helpers.tcl",
308309
"replace_hier_mod1.v",
310+
"replace_hier_mod6.v",
309311
"replace_hier_mod_undo.tcl",
310312
"replace_hier_mod_undo2.tcl",
311313
"sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib",

‎src/odb/test/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ or_integration_tests(
4747
replace_hier_mod3
4848
replace_hier_mod4
4949
replace_hier_mod5
50+
replace_hier_mod6
5051
replace_hier_mod_report_checks
5152
rounding
5253
row_settings

‎src/odb/test/replace_hier_mod6.ok‎

Lines changed: 283 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,283 @@
1+
[INFO ODB-0227] LEF file: data/sky130hd/sky130_fd_sc_hd.tlef, created 13 layers, 25 vias
2+
[INFO ODB-0227] LEF file: data/sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
3+
[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
4+
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
5+
Startpoint: dpath.b_reg.out[0]$_DFFE_PP_
6+
(rising edge-triggered flip-flop clocked by CLK)
7+
Endpoint: dpath.b_reg.out[0]$_DFFE_PP_
8+
(rising edge-triggered flip-flop clocked by CLK)
9+
Path Group: CLK
10+
Path Type: max
11+
12+
Delay Time Description
13+
---------------------------------------------------------
14+
0.00 0.00 clock CLK (rise edge)
15+
0.00 0.00 clock network delay (ideal)
16+
0.00 0.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
17+
0.35 0.35 ^ dpath.b_reg.out[0]$_DFFE_PP_/Q (sky130_fd_sc_hd__edfxtp_1)
18+
0.00 0.35 ^ _120_/_113_/A (sky130_fd_sc_hd__xor2_1)
19+
0.10 0.45 v _120_/_113_/X (sky130_fd_sc_hd__xor2_1)
20+
0.00 0.45 v _120_/_115_/C (sky130_fd_sc_hd__maj3_1)
21+
0.39 0.83 v _120_/_115_/X (sky130_fd_sc_hd__maj3_1)
22+
0.00 0.83 v _120_/_117_/C (sky130_fd_sc_hd__maj3_1)
23+
0.42 1.25 v _120_/_117_/X (sky130_fd_sc_hd__maj3_1)
24+
0.00 1.25 v _120_/_119_/A2 (sky130_fd_sc_hd__a21oi_1)
25+
0.27 1.52 ^ _120_/_119_/Y (sky130_fd_sc_hd__a21oi_1)
26+
0.00 1.52 ^ _120_/_120_/A2 (sky130_fd_sc_hd__o21ai_0)
27+
0.18 1.70 v _120_/_120_/Y (sky130_fd_sc_hd__o21ai_0)
28+
0.00 1.70 v _120_/_151_/A (sky130_fd_sc_hd__nand2_1)
29+
0.09 1.79 ^ _120_/_151_/Y (sky130_fd_sc_hd__nand2_1)
30+
0.00 1.79 ^ _120_/_158_/C1 (sky130_fd_sc_hd__o211ai_1)
31+
0.61 2.40 v _120_/_158_/Y (sky130_fd_sc_hd__o211ai_1)
32+
0.00 2.40 v _125_/A2 (sky130_fd_sc_hd__o21bai_1)
33+
1.11 3.51 ^ _125_/Y (sky130_fd_sc_hd__o21bai_1)
34+
0.00 3.51 ^ dpath.b_reg.out[0]$_DFFE_PP_/DE (sky130_fd_sc_hd__edfxtp_1)
35+
3.51 data arrival time
36+
37+
1.00 1.00 clock CLK (rise edge)
38+
0.00 1.00 clock network delay (ideal)
39+
0.00 1.00 clock reconvergence pessimism
40+
1.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
41+
-0.39 0.61 library setup time
42+
0.61 data required time
43+
---------------------------------------------------------
44+
0.61 data required time
45+
-3.51 data arrival time
46+
---------------------------------------------------------
47+
-2.90 slack (VIOLATED)
48+
49+
50+
Cell type report for _120_ (ALU_16_HAN_CARLSON)
51+
Cell type report: Count Area
52+
Inverter 1 3.75
53+
Multi-Input combinational cell 106 746.97
54+
Total 107 750.72
55+
56+
=============================================
57+
ALU_16_HAN_CARLSON -> ALU_16_BRENT_KUNG
58+
=============================================
59+
Successfully replaced hier module
60+
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
61+
Startpoint: dpath.b_reg.out[0]$_DFFE_PP_
62+
(rising edge-triggered flip-flop clocked by CLK)
63+
Endpoint: dpath.b_reg.out[0]$_DFFE_PP_
64+
(rising edge-triggered flip-flop clocked by CLK)
65+
Path Group: CLK
66+
Path Type: max
67+
68+
Delay Time Description
69+
---------------------------------------------------------
70+
0.00 0.00 clock CLK (rise edge)
71+
0.00 0.00 clock network delay (ideal)
72+
0.00 0.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
73+
0.35 0.35 ^ dpath.b_reg.out[0]$_DFFE_PP_/Q (sky130_fd_sc_hd__edfxtp_1)
74+
0.00 0.35 ^ _120_/_101_/A (sky130_fd_sc_hd__xor2_1)
75+
0.10 0.45 v _120_/_101_/X (sky130_fd_sc_hd__xor2_1)
76+
0.00 0.45 v _120_/_103_/C (sky130_fd_sc_hd__maj3_1)
77+
0.39 0.83 v _120_/_103_/X (sky130_fd_sc_hd__maj3_1)
78+
0.00 0.83 v _120_/_105_/C (sky130_fd_sc_hd__maj3_1)
79+
0.40 1.23 v _120_/_105_/X (sky130_fd_sc_hd__maj3_1)
80+
0.00 1.23 v _120_/_113_/A1 (sky130_fd_sc_hd__a31oi_1)
81+
0.24 1.48 ^ _120_/_113_/Y (sky130_fd_sc_hd__a31oi_1)
82+
0.00 1.48 ^ _120_/_131_/A1 (sky130_fd_sc_hd__o41ai_1)
83+
0.19 1.67 v _120_/_131_/Y (sky130_fd_sc_hd__o41ai_1)
84+
0.00 1.67 v _120_/_134_/A2 (sky130_fd_sc_hd__a31o_1)
85+
0.27 1.94 v _120_/_134_/X (sky130_fd_sc_hd__a31o_1)
86+
0.00 1.94 v _120_/_135_/A2 (sky130_fd_sc_hd__a21oi_1)
87+
0.20 2.14 ^ _120_/_135_/Y (sky130_fd_sc_hd__a21oi_1)
88+
0.00 2.14 ^ _120_/_136_/A2 (sky130_fd_sc_hd__o21ai_0)
89+
0.14 2.28 v _120_/_136_/Y (sky130_fd_sc_hd__o21ai_0)
90+
0.00 2.28 v _120_/_138_/C (sky130_fd_sc_hd__maj3_1)
91+
0.68 2.96 v _120_/_138_/X (sky130_fd_sc_hd__maj3_1)
92+
0.00 2.96 v _125_/A2 (sky130_fd_sc_hd__o21bai_1)
93+
0.95 3.91 ^ _125_/Y (sky130_fd_sc_hd__o21bai_1)
94+
0.00 3.91 ^ dpath.b_reg.out[0]$_DFFE_PP_/DE (sky130_fd_sc_hd__edfxtp_1)
95+
3.91 data arrival time
96+
97+
1.00 1.00 clock CLK (rise edge)
98+
0.00 1.00 clock network delay (ideal)
99+
0.00 1.00 clock reconvergence pessimism
100+
1.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
101+
-0.39 0.61 library setup time
102+
0.61 data required time
103+
---------------------------------------------------------
104+
0.61 data required time
105+
-3.91 data arrival time
106+
---------------------------------------------------------
107+
-3.31 slack (VIOLATED)
108+
109+
110+
Cell type report for _120_ (ALU_16_BRENT_KUNG)
111+
Cell type report: Count Area
112+
Multi-Input combinational cell 92 658.13
113+
Total 92 658.13
114+
Repair timing output passed/skipped equivalence test
115+
116+
=============================================
117+
ALU_16_BRENT_KUNG -> ALU_16_KOGGE_STONE
118+
=============================================
119+
Successfully replaced hier module
120+
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
121+
Startpoint: dpath.b_reg.out[0]$_DFFE_PP_
122+
(rising edge-triggered flip-flop clocked by CLK)
123+
Endpoint: dpath.b_reg.out[0]$_DFFE_PP_
124+
(rising edge-triggered flip-flop clocked by CLK)
125+
Path Group: CLK
126+
Path Type: max
127+
128+
Delay Time Description
129+
---------------------------------------------------------
130+
0.00 0.00 clock CLK (rise edge)
131+
0.00 0.00 clock network delay (ideal)
132+
0.00 0.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
133+
0.38 0.38 v dpath.b_reg.out[0]$_DFFE_PP_/Q (sky130_fd_sc_hd__edfxtp_1)
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0.00 0.38 v _120_/_158_/A (sky130_fd_sc_hd__xnor2_1)
135+
0.17 0.56 v _120_/_158_/Y (sky130_fd_sc_hd__xnor2_1)
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0.00 0.56 v _120_/_160_/C (sky130_fd_sc_hd__maj3_1)
137+
0.41 0.96 v _120_/_160_/X (sky130_fd_sc_hd__maj3_1)
138+
0.00 0.96 v _120_/_163_/A1 (sky130_fd_sc_hd__o21ai_0)
139+
0.31 1.28 ^ _120_/_163_/Y (sky130_fd_sc_hd__o21ai_0)
140+
0.00 1.28 ^ _120_/_166_/A2 (sky130_fd_sc_hd__a21oi_1)
141+
0.16 1.43 v _120_/_166_/Y (sky130_fd_sc_hd__a21oi_1)
142+
0.00 1.43 v _120_/_167_/A2 (sky130_fd_sc_hd__o21ai_0)
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0.25 1.69 ^ _120_/_167_/Y (sky130_fd_sc_hd__o21ai_0)
144+
0.00 1.69 ^ _120_/_205_/A1 (sky130_fd_sc_hd__a21o_1)
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0.63 2.32 ^ _120_/_205_/X (sky130_fd_sc_hd__a21o_1)
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0.00 2.32 ^ _125_/A2 (sky130_fd_sc_hd__o21bai_1)
147+
0.49 2.81 v _125_/Y (sky130_fd_sc_hd__o21bai_1)
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0.00 2.81 v dpath.b_reg.out[0]$_DFFE_PP_/DE (sky130_fd_sc_hd__edfxtp_1)
149+
2.81 data arrival time
150+
151+
1.00 1.00 clock CLK (rise edge)
152+
0.00 1.00 clock network delay (ideal)
153+
0.00 1.00 clock reconvergence pessimism
154+
1.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
155+
-0.38 0.62 library setup time
156+
0.62 data required time
157+
---------------------------------------------------------
158+
0.62 data required time
159+
-2.81 data arrival time
160+
---------------------------------------------------------
161+
-2.19 slack (VIOLATED)
162+
163+
164+
Cell type report for _120_ (ALU_16_KOGGE_STONE)
165+
Cell type report: Count Area
166+
Inverter 2 7.51
167+
Multi-Input combinational cell 143 994.70
168+
Total 145 1002.21
169+
Repair timing output passed/skipped equivalence test
170+
171+
=============================================
172+
ALU_16_KOGGE_STONE -> ALU_16_SKLANSKY
173+
=============================================
174+
Successfully replaced hier module
175+
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
176+
Startpoint: dpath.b_reg.out[0]$_DFFE_PP_
177+
(rising edge-triggered flip-flop clocked by CLK)
178+
Endpoint: dpath.b_reg.out[0]$_DFFE_PP_
179+
(rising edge-triggered flip-flop clocked by CLK)
180+
Path Group: CLK
181+
Path Type: max
182+
183+
Delay Time Description
184+
---------------------------------------------------------
185+
0.00 0.00 clock CLK (rise edge)
186+
0.00 0.00 clock network delay (ideal)
187+
0.00 0.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
188+
0.38 0.38 v dpath.b_reg.out[0]$_DFFE_PP_/Q (sky130_fd_sc_hd__edfxtp_1)
189+
0.00 0.38 v _120_/_116_/A (sky130_fd_sc_hd__xor2_1)
190+
0.23 0.62 ^ _120_/_116_/X (sky130_fd_sc_hd__xor2_1)
191+
0.00 0.62 ^ _120_/_118_/C (sky130_fd_sc_hd__maj3_1)
192+
0.24 0.86 ^ _120_/_118_/X (sky130_fd_sc_hd__maj3_1)
193+
0.00 0.86 ^ _120_/_120_/C (sky130_fd_sc_hd__maj3_1)
194+
0.22 1.08 ^ _120_/_120_/X (sky130_fd_sc_hd__maj3_1)
195+
0.00 1.08 ^ _120_/_129_/A1 (sky130_fd_sc_hd__a31o_1)
196+
0.21 1.28 ^ _120_/_129_/X (sky130_fd_sc_hd__a31o_1)
197+
0.00 1.28 ^ _120_/_147_/A1 (sky130_fd_sc_hd__a31o_1)
198+
0.28 1.56 ^ _120_/_147_/X (sky130_fd_sc_hd__a31o_1)
199+
0.00 1.56 ^ _120_/_152_/A1 (sky130_fd_sc_hd__a21boi_0)
200+
0.16 1.72 v _120_/_152_/Y (sky130_fd_sc_hd__a21boi_0)
201+
0.00 1.72 v _120_/_153_/A2 (sky130_fd_sc_hd__o21ai_0)
202+
1.84 3.56 ^ _120_/_153_/Y (sky130_fd_sc_hd__o21ai_0)
203+
0.00 3.56 ^ _125_/A2 (sky130_fd_sc_hd__o21bai_1)
204+
0.84 4.39 v _125_/Y (sky130_fd_sc_hd__o21bai_1)
205+
0.00 4.39 v dpath.b_reg.out[0]$_DFFE_PP_/DE (sky130_fd_sc_hd__edfxtp_1)
206+
4.39 data arrival time
207+
208+
1.00 1.00 clock CLK (rise edge)
209+
0.00 1.00 clock network delay (ideal)
210+
0.00 1.00 clock reconvergence pessimism
211+
1.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
212+
-0.47 0.53 library setup time
213+
0.53 data required time
214+
---------------------------------------------------------
215+
0.53 data required time
216+
-4.39 data arrival time
217+
---------------------------------------------------------
218+
-3.86 slack (VIOLATED)
219+
220+
221+
Cell type report for _120_ (ALU_16_SKLANSKY)
222+
Cell type report: Count Area
223+
Inverter 3 11.26
224+
Multi-Input combinational cell 99 715.69
225+
Total 102 726.95
226+
Repair timing output passed/skipped equivalence test
227+
228+
=============================================
229+
ALU_16_SKLANSKY -> ALU_16_HAN_CARLSON
230+
=============================================
231+
Successfully replaced hier module
232+
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
233+
Startpoint: dpath.b_reg.out[0]$_DFFE_PP_
234+
(rising edge-triggered flip-flop clocked by CLK)
235+
Endpoint: dpath.b_reg.out[0]$_DFFE_PP_
236+
(rising edge-triggered flip-flop clocked by CLK)
237+
Path Group: CLK
238+
Path Type: max
239+
240+
Delay Time Description
241+
---------------------------------------------------------
242+
0.00 0.00 clock CLK (rise edge)
243+
0.00 0.00 clock network delay (ideal)
244+
0.00 0.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
245+
0.35 0.35 ^ dpath.b_reg.out[0]$_DFFE_PP_/Q (sky130_fd_sc_hd__edfxtp_1)
246+
0.00 0.35 ^ _120_/_113_/A (sky130_fd_sc_hd__xor2_1)
247+
0.10 0.45 v _120_/_113_/X (sky130_fd_sc_hd__xor2_1)
248+
0.00 0.45 v _120_/_115_/C (sky130_fd_sc_hd__maj3_1)
249+
0.39 0.83 v _120_/_115_/X (sky130_fd_sc_hd__maj3_1)
250+
0.00 0.83 v _120_/_117_/C (sky130_fd_sc_hd__maj3_1)
251+
0.42 1.25 v _120_/_117_/X (sky130_fd_sc_hd__maj3_1)
252+
0.00 1.25 v _120_/_119_/A2 (sky130_fd_sc_hd__a21oi_1)
253+
0.27 1.52 ^ _120_/_119_/Y (sky130_fd_sc_hd__a21oi_1)
254+
0.00 1.52 ^ _120_/_120_/A2 (sky130_fd_sc_hd__o21ai_0)
255+
0.18 1.70 v _120_/_120_/Y (sky130_fd_sc_hd__o21ai_0)
256+
0.00 1.70 v _120_/_151_/A (sky130_fd_sc_hd__nand2_1)
257+
0.09 1.79 ^ _120_/_151_/Y (sky130_fd_sc_hd__nand2_1)
258+
0.00 1.79 ^ _120_/_158_/C1 (sky130_fd_sc_hd__o211ai_1)
259+
0.61 2.40 v _120_/_158_/Y (sky130_fd_sc_hd__o211ai_1)
260+
0.00 2.40 v _125_/A2 (sky130_fd_sc_hd__o21bai_1)
261+
1.11 3.51 ^ _125_/Y (sky130_fd_sc_hd__o21bai_1)
262+
0.00 3.51 ^ dpath.b_reg.out[0]$_DFFE_PP_/DE (sky130_fd_sc_hd__edfxtp_1)
263+
3.51 data arrival time
264+
265+
1.00 1.00 clock CLK (rise edge)
266+
0.00 1.00 clock network delay (ideal)
267+
0.00 1.00 clock reconvergence pessimism
268+
1.00 ^ dpath.b_reg.out[0]$_DFFE_PP_/CLK (sky130_fd_sc_hd__edfxtp_1)
269+
-0.39 0.61 library setup time
270+
0.61 data required time
271+
---------------------------------------------------------
272+
0.61 data required time
273+
-3.51 data arrival time
274+
---------------------------------------------------------
275+
-2.90 slack (VIOLATED)
276+
277+
278+
Cell type report for _120_ (ALU_16_HAN_CARLSON)
279+
Cell type report: Count Area
280+
Inverter 1 3.75
281+
Multi-Input combinational cell 106 746.97
282+
Total 107 750.72
283+
Repair timing output passed/skipped equivalence test

‎src/odb/test/replace_hier_mod6.tcl‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
#
2+
# replace_hier_mod6
3+
#
4+
# Used a new gcd design (synthesized by Yosys v0.58) for test.
5+
# - Test if uninstantiated module can be swapped.
6+
# - Test if four different ALUs (HC, BK, KS, SK) have equivalent functions.
7+
# - Test if setup timing is the same after the swap (HC->BK->KS->SK->HC).
8+
#
9+
source "helpers.tcl"
10+
11+
set test_name replace_hier_mod6
12+
13+
read_lef "data/sky130hd/sky130_fd_sc_hd.tlef"
14+
read_lef "data/sky130hd/sky130_fd_sc_hd_merged.lef"
15+
16+
read_liberty "sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib"
17+
#set_debug_level ODB dbReadVerilog 1
18+
#set_debug_level ODB replace_design 1
19+
read_verilog $test_name.v
20+
link_design -hier gcd
21+
create_clock -name CLK -period 1 clk
22+
23+
# _001_ is a critical ALU output.
24+
# _120_ is an ALU instance.
25+
estimate_parasitics -placement
26+
report_checks -fields input_pins -through _001_
27+
report_cell_usage _120_
28+
29+
# For eqy, write a verilog before replace_hier_module
30+
# - EQ check is disabled in the regression due ot its excessive runtime.
31+
# - To enable the EQ check, you should set the envar "EQUIVALENCE_CHECK".
32+
write_verilog_for_eqy $test_name before "None"
33+
34+
proc do_swap { from_alu to_alu } {
35+
variable test_name
36+
puts "\n============================================="
37+
puts "$from_alu -> $to_alu"
38+
puts "============================================="
39+
set result [catch { replace_hier_module _120_ $to_alu }]
40+
if { $result == 0 } {
41+
puts "Successfully replaced hier module"
42+
sta::network_changed
43+
estimate_parasitics -placement
44+
report_checks -fields input_pins -through _001_
45+
report_cell_usage _120_
46+
run_equivalence_test $test_name ./sky130hd/work_around_yosys/ "None"
47+
} else {
48+
puts "Failed to replace hier module"
49+
}
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}
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# Swap ALU module sequence: HC (initial) -> BK -> KS -> SK -> HC
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set alus [list \
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"ALU_16_HAN_CARLSON" \
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"ALU_16_BRENT_KUNG" \
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"ALU_16_KOGGE_STONE" \
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"ALU_16_SKLANSKY" \
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"ALU_16_HAN_CARLSON" \
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]
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for {set i 0} {$i < [llength $alus] - 1} {incr i} {
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do_swap [lindex $alus $i] [lindex $alus [expr {$i + 1}]]
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}

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