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[LoongArch][NFC] Add tests for vector type nor 
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  • llvm/test/CodeGen/LoongArch

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‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @nor_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
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%v2 = or <32 x i8> %v0, %v1
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%v3 = xor <32 x i8> %v2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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store <32 x i8> %v3, ptr %res
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ret void
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}
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define void @nor_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
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%v2 = or <16 x i16> %v0, %v1
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%v3 = xor <16 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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store <16 x i16> %v3, ptr %res
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ret void
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}
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define void @nor_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = or <8 x i32> %v0, %v1
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%v3 = xor <8 x i32> %v2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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store <8 x i32> %v3, ptr %res
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ret void
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}
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define void @nor_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = or <4 x i64> %v0, %v1
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%v3 = xor <4 x i64> %v2, <i64 -1, i64 -1, i64 -1, i64 -1>
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store <4 x i64> %v3, ptr %res
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ret void
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}
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define void @nor_u_v32i8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr1, 31
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = or <32 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
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%v2 = xor <32 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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store <32 x i8> %v2, ptr %res
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ret void
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}
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define void @nor_u_v16i16(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvrepli.h $xr1, 31
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = or <16 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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%v2 = xor <16 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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store <16 x i16> %v2, ptr %res
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ret void
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}
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define void @nor_u_v8i32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvrepli.w $xr1, 31
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = or <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%v2 = xor <8 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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store <8 x i32> %v2, ptr %res
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ret void
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}
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define void @nor_u_v4i64(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvrepli.d $xr1, 31
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; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = or <4 x i64> %v0, <i64 31, i64 31, i64 31, i64 31>
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%v2 = xor <4 x i64> %v1, <i64 -1, i64 -1, i64 -1, i64 -1>
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store <4 x i64> %v2, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll‎

Lines changed: 135 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @nor_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = or <16 x i8> %v0, %v1
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%v3 = xor <16 x i8> %v2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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store <16 x i8> %v3, ptr %res
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ret void
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}
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define void @nor_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = or <8 x i16> %v0, %v1
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%v3 = xor <8 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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store <8 x i16> %v3, ptr %res
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ret void
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}
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define void @nor_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = or <4 x i32> %v0, %v1
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%v3 = xor <4 x i32> %v2, <i32 -1, i32 -1, i32 -1, i32 -1>
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store <4 x i32> %v3, ptr %res
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ret void
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}
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define void @nor_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: nor_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = or <2 x i64> %v0, %v1
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%v3 = xor <2 x i64> %v2, <i64 -1, i64 -1>
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store <2 x i64> %v3, ptr %res
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ret void
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}
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define void @nor_u_v16i8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.b $vr1, 31
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = or <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
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%v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @nor_u_v8i16(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.h $vr1, 31
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = or <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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%v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @nor_u_v4i32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.w $vr1, 31
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = or <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
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%v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @nor_u_v2i64(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: nor_u_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.d $vr1, 31
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = or <2 x i64> %v0, <i64 31, i64 31>
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%v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
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store <2 x i64> %v2, ptr %res
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ret void
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}

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