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1 parent 787efa7 commit 60cd76bCopy full SHA for 60cd76b
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3562,9 +3562,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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unsigned Factor = Node->getNumOperands();
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if (Factor <= 2 || !isPowerOf2_32(Factor))
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break;
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- SmallVector<SDValue, 8> Ops;
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- for (SDValue Op : Node->ops())
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- Ops.push_back(Op);
+ SmallVector<SDValue, 8> Ops(Node->ops());
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EVT VecVT = Node->getValueType(0);
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SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
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// Deinterleave at Factor/2 so each result contains two factors interleaved:
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