Merge pull request Xilinx#1284 from Xilinx/preusser/q_srl_guard

Guard Q_srl against Instantiation with a Depth below Two

Author: auphelia

finn-rtllib/fifo/hdl/Q_srl.v

@@ -119,6 +119,15 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
    reg       i_b_reg  		    // - true iff !full
 	     /* synthesis syn_allow_retiming=0 */ ;
 
+	// Parameter Checking
+	initial begin
+		if(depth < 2) begin
+			$error("%m: FIFO depth must be two or higher.");
+			$finish;
+		end
+	end
+
+
    assign addr_full_ = (state_==state_more) && (addr_==depth-2);
 						// - queue full
    assign addr_zero_ = (addr==0);		// - queue contains 2 (or 1,0)

finn-rtllib/memstream/hdl/Q_srl.v

@@ -539,7 +539,7 @@ def decompose_pow2(x):
     ret_final = []
     for cand_depth in ret_pass2:
         if cand_depth <= max_qsrl_depth:
-            ret_final.append((cand_depth, "rtl"))
+            ret_final.append((max(2, cand_depth), "rtl"))
         else:
             ret_final.append((cand_depth, "vivado"))
 

src/finn/transformation/fpgadataflow/set_fifo_depths.py

@@ -63,7 +63,7 @@ def get_folding_cfg(depth=65536):
 @pytest.mark.slow
 @pytest.mark.vivado
 @pytest.mark.fpgadataflow
-@pytest.mark.parametrize("depth", [16384, 65536, 45000])
+@pytest.mark.parametrize("depth", [16384, 65536, 45000, 1537])
 @pytest.mark.parametrize("force_python_rtlsim", ["True", "False"])
 def test_split_large_fifos(depth, force_python_rtlsim):
     tmp_output_dir = fetch_test_model("tfc")
@@ -103,13 +103,14 @@ def test_split_large_fifos(depth, force_python_rtlsim):
         inst = getCustomOp(fifo_node)
         fifo_depth = inst.get_nodeattr("depth")
         assert fifo_depth == golden_cfg[i % len(golden_cfg)][0]
+        assert fifo_depth > 1
 
     shutil.rmtree(tmp_output_dir)
 
 
 def test_split_large_fifo_configs():
     ret0 = get_fifo_split_configs(513, 256, 32768)
-    assert ret0 == [(512, "vivado"), (1, "rtl")]
+    assert ret0 == [(512, "vivado"), (2, "rtl")]
     ret1 = get_fifo_split_configs(1200, 256, 32768)
     assert ret1 == [(1024, "vivado"), (176, "rtl")]
     ret2 = get_fifo_split_configs(45000, 256, 32768)