Enable PLL1 with basic setpoint support

Enable the PLL_LDO in all setpoints, and enable PLL1 in setpoint 1.
Since I'm only using setpoints for PLL_LDO and PLL1 bring-up, I'm
implementing the rest of the GPC state machine in software (specifically
for the ENET clocks). This seems sufficient for enabling PLL1 and
getting a clean 50MHz ENET reference clock. I can increase the ENET
transfer speeds in the MAC and PHY.

The GPC, PMU, and CCM APIs are a bare-minimal. They should be introduced
in a separate commit / PR. But they're good enough for prototyping.

Author: mciantyre

board/src/imxrt1170evk-cm7.rs

@@ -40,6 +40,9 @@ const CLOCK_GATES: &[clock_gate::Locator] = &[
     clock_gate::flexpwm::<{ PWM_INSTANCE }>(),
     clock_gate::lpi2c::<{ I2C_INSTANCE }>(),
     clock_gate::snvs(),
+];
+
+const ENET_CLOCK_GATES: &[clock_gate::Locator] = &[
     clock_gate::enet(),
     clock_gate::enet_1g(),
     clock_gate::enet_qos(),
@@ -48,10 +51,49 @@ const CLOCK_GATES: &[clock_gate::Locator] = &[
 pub(crate) unsafe fn configure() {
     let mut ccm = ral::ccm::CCM::instance();
 
+    let gpc = unsafe { ral::gpc_cpu_mode_ctrl_::GPC_CPU_MODE_CTRL_0::instance() };
+    let gpc = &*gpc;
+    let pll = unsafe { ral::anadig_pll::ANADIG_PLL::instance() };
+    let mut pmu = unsafe { ral::anadig_pmu::ANADIG_PMU::instance() };
+
+    hal::pmu::enable_pll_reference_voltage(&mut pmu, true);
+    hal::pmu::set_phy_ldo_setpoints(&mut pmu, hal::pmu::Setpoint::all());
+    hal::pmu::set_phy_ldo_control(&mut pmu, hal::pmu::ControlMode::Gpc);
+    hal::pmu::set_pll_reference_control(&mut pmu, hal::pmu::ControlMode::Gpc);
+
+    for clock_source in {
+        use hal::ccm::ClockSource::*;
+        [Pll1, Pll1Clk, Pll1Div2, Pll1Div5]
+    } {
+        let oscpll = &ccm.OSCPLL[clock_source as usize];
+        ral::write_reg!(ral::ccm::oscpll, oscpll, OSCPLL_DIRECT, 0);
+        hal::ccm::set_setpoints(&mut ccm, clock_source, hal::ccm::Setpoint::SP1);
+        hal::ccm::set_gpc_control_mode(&mut ccm, clock_source, hal::ccm::ControlMode::Gpc).unwrap();
+    }
+
+    ral::modify_reg!(ral::anadig_pll, pll, SYS_PLL1_CTRL,
+        SYS_PLL1_CONTROL_MODE: 1,
+        SYS_PLL1_DIV2_CONTROL_MODE: 1,
+        SYS_PLL1_DIV5_CONTROL_MODE: 1,
+    );
+
     prepare_clock_tree(&mut ccm);
     CLOCK_GATES
         .iter()
         .for_each(|locator| locator.set(&mut ccm, clock_gate::ON));
+
+    ENET_CLOCK_GATES
+        .iter()
+        .for_each(|l| l.set(&mut ccm, clock_gate::OFF));
+    clock_tree::enet_root_on(&mut ccm, false);
+
+    clock_tree::configure_enet(RUN_MODE, &mut ccm);
+    hal::gpc::request_setpoint_transition(gpc, 1).unwrap();
+
+    clock_tree::enet_root_on(&mut ccm, true);
+    ENET_CLOCK_GATES
+        .iter()
+        .for_each(|l| l.set(&mut ccm, clock_gate::ON));
 }
 
 fn prepare_clock_tree(ccm: &mut ral::ccm::CCM) {
@@ -61,7 +103,6 @@ fn prepare_clock_tree(ccm: &mut ral::ccm::CCM) {
     clock_tree::configure_lpuart::<{ CONSOLE_INSTANCE }>(RUN_MODE, ccm);
     clock_tree::configure_lpspi::<SPI_INSTANCE>(RUN_MODE, ccm);
     clock_tree::configure_lpi2c::<{ I2C_INSTANCE }>(RUN_MODE, ccm);
-    clock_tree::configure_enet(RUN_MODE, ccm);
 }
 
 pub const PIT_FREQUENCY: u32 = clock_tree::bus_frequency(RUN_MODE);
@@ -441,7 +482,7 @@ fn init_enet_phy_ksz8081rnb<
     mdio.write(
         KSZ8081_PHY_ADDR,
         PHY_AUTONEG_ADVERTISE_REG,
-        (AutoNegotiation::BASETX_10_FULL_DUPLEX | AutoNegotiation::IEEE802_3_SELECTOR).bits(),
+        (AutoNegotiation::BASETX_100_FULL_DUPLEX | AutoNegotiation::IEEE802_3_SELECTOR).bits(),
     )
     .unwrap();
     mdio.write(

board/src/imxrt11xx/clock_tree.rs

@@ -29,6 +29,8 @@ enum ClockSource {
     /// SYS_PLL1, with dedicated 1GHz frequency
     /// for ETH.
     SysPll1,
+    /// SYS_PLL1 with a fixed divide-by-2.
+    SysPll1Div2,
     /// SYS_PLL2, main PLL (no PFDs).
     SysPll2,
     /// SYS_PLL3, main PLL (no PDFs).
@@ -50,6 +52,7 @@ impl ClockSource {
         match (self, run_mode) {
             (ClockSource::ArmCm7, RunMode::Overdrive) => 1_000_000_000, // Brr...
             (ClockSource::SysPll1, _) => 1_000_000_000,
+            (ClockSource::SysPll1Div2, _) => 1_000_000_000 / 2,
             (ClockSource::SysPll2, _) => 528_000_000,
             (ClockSource::SysPll3, _) => 480_000_000,
             (ClockSource::XtalOsc24MHz, _) => XTAL_OSCILLATOR_HZ,
@@ -107,6 +110,12 @@ fn configure_clock_root(offset: usize, selection: &Selection, ccm: &mut CCM) {
     ) {}
 }
 
+#[inline(always)]
+fn clock_root_on(offset: usize, ccm: &mut CCM, on: bool) {
+    let clock_root = &ccm.CLOCK_ROOT[offset];
+    ral::modify_reg!(ral::ccm::clockroot, clock_root, CLOCK_ROOT_CONTROL, OFF: !on as u32);
+}
+
 /// Set the bus clock (IPG) configuration for the Cortex M7.
 ///
 /// When this call returns, the bus clock frequency matches the value returned
@@ -266,17 +275,24 @@ where
 
 pub const ENET1_FREQUENCY: u32 = 50_000_000;
 
+/// Turn on / off all ENET root clocks.
+pub fn enet_root_on(ccm: &mut CCM, on: bool) {
+    for offset in 51..=57 {
+        clock_root_on(offset, ccm, on);
+    }
+}
+
 /// Configure clocks for all-things ETH.
 ///
 /// When this call returns, the ENET clock frequencies matches the value returned
 /// by [`enet_frequency`].
 pub fn configure_enet(run_mode: RunMode, ccm: &mut CCM) {
-    const ENET1_ROOT_CLOCK_SOURCE: ClockSource = ClockSource::RcOsc400MHz;
+    const ENET1_ROOT_CLOCK_SOURCE: ClockSource = ClockSource::SysPll1Div2;
     let enet1_divider: u32 = ENET1_ROOT_CLOCK_SOURCE.frequency(run_mode) / ENET1_FREQUENCY;
     configure_clock_root(
         51,
         &Selection {
-            mux: 0b010,
+            mux: 4,
             source: ENET1_ROOT_CLOCK_SOURCE,
             divider: enet1_divider,
         },

examples/rtic_enet_dhcp_tcp.rs

@@ -154,7 +154,7 @@ mod app {
         dev.set_duplex(hal::enet::Duplex::Full);
         dev.enable_mib(true);
         dev.enable_rmii_mode(true);
-        dev.enable_10t_mode(true);
+        dev.enable_10t_mode(false);
         dev.enable_mac(true);
 
         let mut time: i64 = 0;

src/chip/imxrt11xx.rs

@@ -5,6 +5,8 @@
 pub mod ccm;
 #[path = "dma.rs"]
 pub mod dma;
+pub mod gpc;
+pub mod pmu;
 pub mod usbphy;
 
 cfg_if::cfg_if! {
@@ -15,7 +17,7 @@ cfg_if::cfg_if! {
 }
 
 pub(crate) mod reexports {
-    pub use super::usbphy;
+    pub use super::{gpc, pmu, usbphy};
 }
 
 pub(crate) mod iomuxc {

src/chip/imxrt11xx/ccm.rs

@@ -10,3 +10,68 @@ pub mod clock_gate;
 pub mod output_source;
 
 pub use crate::common::ccm::XTAL_OSCILLATOR_HZ;
+
+pub use crate::gpc::{ControlMode, Setpoint};
+use crate::ral::{self, ccm::CCM};
+
+/// A clock source.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(usize)]
+#[non_exhaustive]
+pub enum ClockSource {
+    /// The voltage controlled oscillator for PLL1.
+    ///
+    /// This output isn't exposed by the clock tree.
+    /// However, the [`Pll1Clk`] is exposed.
+    Pll1 = 21,
+    /// The PLL1 output into the clock tree.
+    Pll1Clk = 22,
+    /// PLL1 with a fixed divide-by-2.
+    Pll1Div2 = 23,
+    /// PLL1 with a fixed divide-by-5.
+    Pll1Div5 = 24,
+}
+
+/// Indicates that the clock does not support setpoint control.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct SetpointNotImplementedError(());
+
+/// Signals if the clock source supports setpoint control.
+#[inline]
+pub fn has_setpoint(ccm: &CCM, clock_source: ClockSource) -> bool {
+    let oscpll = &ccm.OSCPLL[clock_source as usize];
+    ral::read_reg!(
+        ral::ccm::oscpll,
+        oscpll,
+        OSCPLL_CONFIG,
+        SETPOINT_PRESENT == 1
+    )
+}
+
+/// Set the GPC setpoint control mode for the clock source.
+///
+/// Returns an error if [`has_setpoint`] does not report support
+/// for setpoints.
+#[inline]
+pub fn set_gpc_control_mode(
+    ccm: &mut CCM,
+    clock_source: ClockSource,
+    control_mode: ControlMode,
+) -> Result<(), SetpointNotImplementedError> {
+    if control_mode == ControlMode::Gpc && !has_setpoint(ccm, clock_source) {
+        return Err(SetpointNotImplementedError(()));
+    }
+
+    let oscpll = &ccm.OSCPLL[clock_source as usize];
+    ral::modify_reg!(ral::ccm::oscpll, oscpll, OSCPLL_AUTHEN, SETPOINT_MODE: control_mode.is_gpc() as u32);
+    Ok(())
+}
+
+/// Configure the setpoints for the clock.
+///
+/// Note: this does not affect the standby setpoints.
+#[inline]
+pub fn set_setpoints(ccm: &mut CCM, clock_source: ClockSource, setpoint: Setpoint) {
+    let oscpll = &ccm.OSCPLL[clock_source as usize];
+    ral::modify_reg!(ral::ccm::oscpll, oscpll, OSCPLL_SETPOINT, SETPOINT: setpoint.bits() as u32);
+}

src/chip/imxrt11xx/ccm/clock_gate.rs

@@ -3,6 +3,8 @@
 //! This module exposes a similar API as the `clock_gate` API
 //! for the 10xx MCUs. Consult that module's documentation for
 //! more information.
+//!
+//! The API works for clock gates in unassigned mode.
 
 use crate::ral::{self, ccm::CCM};
 

src/chip/imxrt11xx/gpc.rs

@@ -0,0 +1,89 @@
+//! General Power Controller.
+
+use crate::ral::{self, gpc_cpu_mode_ctrl_::RegisterBlock as GpcCtrl};
+
+/// Describes the power / clock control mode.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u32)]
+pub enum ControlMode {
+    /// Software, not the GPC, controls the element.
+    Software,
+    /// The GPC controls the element.
+    Gpc,
+}
+
+impl ControlMode {
+    pub(crate) const fn is_gpc(self) -> bool {
+        matches!(self, Self::Gpc)
+    }
+}
+
+bitflags::bitflags! {
+    /// A bitmask for specifying setpoints.
+    ///
+    /// No matter the API, a high bit indicates that the setpoint
+    /// is "enabled,", "compatible," or "on" for the given configuration.
+    /// A lower bit indicates that the setpoint is "disabled," "not
+    /// compatible," or "off" for the configuration. (Some registers have
+    /// inverted interpretation; nevertheless, the APIs hide this for
+    /// consistency.)
+    pub struct Setpoint: u16 {
+        /// Setpoint 0.
+        const SP0 = 1 << 0;
+        /// Setpoint 1.
+        const SP1 = 1 << 1;
+        /// Setpoint 2.
+        const SP2 = 1 << 2;
+        /// Setpoint 3.
+        const SP3 = 1 << 3;
+        /// Setpoint 4.
+        const SP4 = 1 << 4;
+        /// Setpoint 5.
+        const SP5 = 1 << 5;
+        /// Setpoint 6.
+        const SP6 = 1 << 6;
+        /// Setpoint 7.
+        const SP7 = 1 << 7;
+        /// Setpoint 8.
+        const SP8 = 1 << 8;
+        /// Setpoint 9.
+        const SP9 = 1 << 9;
+        /// Setpoint 10.
+        const SP10 = 1 << 10;
+        /// Setpoint 11.
+        const SP11 = 1 << 11;
+        /// Setpoint 12.
+        const SP12 = 1 << 12;
+        /// Setpoint 13.
+        const SP13 = 1 << 13;
+        /// Setpoint 14.
+        const SP14 = 1 << 14;
+        /// Setpoint 15.
+        const SP15 = 1 << 15;
+    }
+}
+
+/// The setpoint is out of range.
+///
+/// Setpoints are bound between 0 and 15, inclusive.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct SetpointOutOfRangeError(pub u32);
+
+/// Request a run mode setpoint transition.
+///
+/// Blocks until the transition completes.
+pub fn request_setpoint_transition(
+    gpc: &GpcCtrl,
+    setpoint: u32,
+) -> Result<(), SetpointOutOfRangeError> {
+    if setpoint < 16 {
+        ral::modify_reg!(ral::gpc_cpu_mode_ctrl_, gpc, CM_SP_CTRL,
+            CPU_SP_RUN: setpoint,
+            CPU_SP_RUN_EN: 1
+        );
+        while ral::read_reg!(ral::gpc_cpu_mode_ctrl_, gpc, CM_SP_CTRL, CPU_SP_RUN_EN == 1) {}
+        Ok(())
+    } else {
+        Err(SetpointOutOfRangeError(setpoint))
+    }
+}

src/chip/imxrt11xx/pmu.rs

@@ -0,0 +1,45 @@
+//! Power Management Unit.
+//!
+//! The PMu also provides some control for the PHY LDO.
+//! Note that the terms "PHY LDO" and `LDO_PLL` represent
+//! the same thing, and this API prefers the PHY LDO term.
+
+pub use crate::gpc::{ControlMode, Setpoint};
+use crate::ral::{self, anadig_pmu::ANADIG_PMU as PMU};
+
+/// Set the control mode for PHY LDO.
+#[inline]
+pub fn set_phy_ldo_control(pmu: &mut PMU, control_mode: ControlMode) {
+    ral::modify_reg!(ral::anadig_pmu, pmu, PMU_LDO_PLL, LDO_PLL_CONTROL_MODE: control_mode.is_gpc() as u32);
+}
+
+/// Specify with setpoints should turn on the PHY_LDO.
+///
+/// Each high bit indicates that the PHY LDO is on for that setpoint.
+/// See [`Setpoint`] documentation for more information.
+#[inline]
+pub fn set_phy_ldo_setpoints(pmu: &PMU, setpoint: Setpoint) {
+    // Low bit == on.
+    // High bit == off.
+    //
+    // Flip the bits, since each software setpoint bit
+    // suggests "on."
+    ral::write_reg!(
+        ral::anadig_pmu,
+        pmu,
+        LDO_PLL_ENABLE_SP,
+        (!setpoint).bits() as u32
+    );
+}
+
+/// Enable or disable the PLL bandgap reference voltage.
+#[inline]
+pub fn enable_pll_reference_voltage(pmu: &mut PMU, enable: bool) {
+    ral::modify_reg!(ral::anadig_pmu, pmu, PMU_REF_CTRL, EN_PLL_VOL_REF_BUFFER: enable as u32);
+}
+
+/// Set the control mode for the PLL bandgap reference voltage.
+#[inline]
+pub fn set_pll_reference_control(pmu: &mut PMU, control_mode: ControlMode) {
+    ral::modify_reg!(ral::anadig_pmu, pmu, PMU_REF_CTRL, REF_CONTROL_MODE: control_mode.is_gpc() as u32);
+}