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1 parent 1a5ba71 commit 0943b64Copy full SHA for 0943b64
io-sim/src/Control/Monad/IOSim.hs
@@ -473,9 +473,9 @@ compareTraces (Just passing) trace = unsafePerformIO $ do
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return $ SimTrace tpass tidpass tlpass EventThreadSleep $
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wakeup sleeper tidpass fail
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go _ _ fail = fail
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- wakeup sleeper tidpass (SimTrace tfail tidfail tlfail evfail fail')
+ wakeup sleeper tidpass fail@(SimTrace tfail tidfail tlfail evfail fail')
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| tidpass == tidfail =
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- SimTrace tfail tidfail tlfail EventThreadWake fail'
+ SimTrace tfail tidfail tlfail EventThreadWake fail
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| otherwise = unsafePerformIO $ do
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Just (slp,racing) <- readIORef sleeper
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writeIORef sleeper $ Just (slp,Set.insert (tidfail,tlfail) racing)
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