Skip to content

Commit 204d5c0

Browse files
committed
io-sim-por: refactor happensBeforeStep
1 parent 44366dd commit 204d5c0

File tree

2 files changed

+10
-4
lines changed

2 files changed

+10
-4
lines changed

io-sim/src/Control/Monad/IOSim/Types.hs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -642,7 +642,8 @@ setNonTestThread tid@ThreadId{} = tid
642642
newtype TVarId = TVarId Int deriving (Eq, Ord, Enum, Show)
643643
newtype TimeoutId = TimeoutId Int deriving (Eq, Ord, Enum, Show)
644644
newtype ClockId = ClockId [Int] deriving (Eq, Ord, Show)
645-
newtype VectorClock = VectorClock (Map ThreadId Int) deriving Show
645+
newtype VectorClock = VectorClock { getVectorClock :: Map ThreadId Int }
646+
deriving Show
646647

647648
unTimeoutId :: TimeoutId -> Int
648649
unTimeoutId (TimeoutId a) = a

io-sim/src/Control/Monad/IOSimPOR/Internal.hs

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,13 @@ lubVClock (VectorClock m) (VectorClock m') = VectorClock (Map.unionWith max m m'
121121
-- hbfVClock :: VectorClock -> VectorClock -> Bool
122122
-- hbfVClock (VectorClock m) (VectorClock m') = Map.isSubmapOfBy (<=) m m'
123123

124-
hbfStep :: ThreadId -> Int -> VectorClock -> Bool
125-
hbfStep tid tstep (VectorClock m) = Just tstep <= Map.lookup tid m
124+
happensBeforeStep :: Step -- ^ an earlier step
125+
-> Step -- ^ a later step
126+
-> Bool
127+
happensBeforeStep step step' =
128+
Just (stepStep step)
129+
<= Map.lookup (stepThreadId step)
130+
(getVectorClock $ stepVClock step')
126131

127132
labelledTVarId :: TVar s a -> ST s (Labelled TVarId)
128133
labelledTVarId TVar { tvarId, tvarLabel } = (Labelled tvarId) <$> readSTRef tvarLabel
@@ -1357,7 +1362,7 @@ updateRaces newStep@Step{ stepThreadId = tid, stepEffect = newEffect }
13571362
let lessConcurrent = foldr Set.delete concurrent (effectWakeup newEffect) in
13581363
if tid `elem` concurrent then
13591364
let theseStepsRace = not (isTestThreadId tid) && racingSteps step newStep
1360-
happensBefore = hbfStep (stepThreadId step) (stepStep step) (stepVClock newStep)
1365+
happensBefore = happensBeforeStep step newStep
13611366
nondep' | happensBefore = nondep
13621367
| otherwise = newStep : nondep
13631368
-- We will only record the first race with each thread---reversing

0 commit comments

Comments
 (0)