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LCD RGB disco with SDRAM on F7-Discovery
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‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/.gdbinit

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tar ext :3333
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file lcd_ram_demo.elf
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mon reset halt
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foc c

‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/Makefile

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#
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# This file is part of the libopencm3 project.
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#
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# This library is free software: you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with this library. If not, see <http://www.gnu.org/licenses/>.
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#
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OBJS = clock.o \
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sdram.o \
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BINARY = lcd_ram_demo
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LDSCRIPT = ../stm32f7-discovery.ld
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include ../../Makefile.include
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‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/clock.c

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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Chuck McManis <[email protected]>
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* Copyright (C) 2016 Maxime Vincent <[email protected]>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Now this is just the clock setup code from systick-blink as it is the
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* transferrable part.
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*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/systick.h>
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/* Common function descriptions */
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#include "clock.h"
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/* milliseconds since boot */
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static volatile uint32_t system_millis;
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/* Called when systick fires */
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void sys_tick_handler(void)
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{
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system_millis++;
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}
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/* simple sleep for delay milliseconds */
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void msleep(uint32_t delay)
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{
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uint32_t wake = system_millis + delay;
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while (wake > system_millis);
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}
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/* Getter function for the current time */
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uint32_t mtime(void)
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{
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return system_millis;
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}
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/*
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* clock_setup(void)
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*
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* This function sets up both the base board clock rate
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* and a 1khz "system tick" count. The SYSTICK counter is
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* a standard feature of the Cortex-M series.
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*/
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void clock_setup(void)
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{
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/* Base board frequency, set to 216MHz */
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rcc_clock_setup_hse_3v3(&hse_25mhz_3v3[CLOCK_3V3_216MHZ]);
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/* clock rate / 216000 to get 1mS interrupt rate */
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systick_set_reload(216000);
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systick_set_clocksource(STK_CSR_CLKSOURCE_AHB);
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systick_counter_enable();
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/* this done last */
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systick_interrupt_enable();
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}
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‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/clock.h

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/*
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* This include file describes the functions exported by clock.c
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*/
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#ifndef __CLOCK_H
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#define __CLOCK_H
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/*
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* Definitions for functions being abstracted out
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*/
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void msleep(uint32_t);
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uint32_t mtime(void);
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void clock_setup(void);
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#endif /* generic header protector */
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‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/lcd_ram_demo.c

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/* Includes ------------------------------------------------------------------*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/ltdc.h>
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#include "rk043fn48h.h"
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#include "clock.h"
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#include "sdram.h"
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/* Private function prototypes -----------------------------------------------*/
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static void lcd_config(void);
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static void lcd_pinmux(void);
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static void lcd_clock(void);
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static void lcd_config_layer(void);
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/* Private functions ---------------------------------------------------------*/
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void lcd_pinmux(void)
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{
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/* Enable the LTDC Clock */
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rcc_periph_clock_enable(RCC_LTDC);
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/* Enable GPIOs clock */
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rcc_periph_clock_enable(RCC_GPIOE);
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rcc_periph_clock_enable(RCC_GPIOG);
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rcc_periph_clock_enable(RCC_GPIOI);
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rcc_periph_clock_enable(RCC_GPIOJ);
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rcc_periph_clock_enable(RCC_GPIOK);
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/*** LTDC Pins configuration ***/
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gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO4);
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gpio_set_output_options(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO4);
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gpio_set_af(GPIOE, GPIO_AF14, GPIO4);
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/* GPIOG configuration */
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gpio_mode_setup(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO12);
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gpio_set_output_options(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO12);
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gpio_set_af(GPIOG, GPIO_AF9, GPIO12);
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/* GPIOI LTDC alternate configuration */
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gpio_mode_setup(GPIOI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15);
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gpio_set_output_options(GPIOI, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15);
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gpio_set_af(GPIOI, GPIO_AF14, GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15);
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/* GPIOJ configuration */
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gpio_mode_setup(GPIOJ, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 |
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GPIO5 | GPIO6 | GPIO7 | GPIO8 | GPIO9 |
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GPIO10 | GPIO11 | GPIO13 | GPIO14 | GPIO15);
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gpio_set_output_options(GPIOJ, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 |
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GPIO5 | GPIO6 | GPIO7 | GPIO8 | GPIO9 |
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GPIO10 | GPIO11 | GPIO13 | GPIO14 | GPIO15);
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gpio_set_af(GPIOJ, GPIO_AF14, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 |
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GPIO5 | GPIO6 | GPIO7 | GPIO8 | GPIO9 |
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GPIO10 | GPIO11 | GPIO13 | GPIO14 | GPIO15);
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/* GPIOK configuration */
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gpio_mode_setup(GPIOK, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0 | GPIO1 | GPIO2 | GPIO4 | GPIO5 | GPIO6 | GPIO7);
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gpio_set_output_options(GPIOK, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO0 | GPIO1 | GPIO2 | GPIO4 | GPIO5 | GPIO6 | GPIO7);
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gpio_set_af(GPIOK, GPIO_AF14, GPIO0 | GPIO1 | GPIO2 | GPIO4 | GPIO5 | GPIO6 | GPIO7);
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/* LCD_DISP GPIO configuration */
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gpio_mode_setup(GPIOI, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO12);
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gpio_set_output_options(GPIOI, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO12);
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/* LCD_BL_CTRL GPIO configuration */
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gpio_mode_setup(GPIOK, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
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gpio_set_output_options(GPIOK, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO3);
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/* Assert display enable LCD_DISP pin */
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gpio_set(GPIOI, GPIO12);
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/* Assert backlight LCD_BL_CTRL pin */
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gpio_set(GPIOK, GPIO3);
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}
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static void lcd_config_layer(void)
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{
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/* Windowing configuration */
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ltdc_setup_windowing(LTDC_LAYER_2, 480, 272);
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/* Specifies the pixel format */
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ltdc_set_pixel_format(LTDC_LAYER_2, LTDC_LxPFCR_RGB565);
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/* Default color values */
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ltdc_set_default_colors(LTDC_LAYER_2, 0, 0, 0, 0);
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/* Constant alpha */
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ltdc_set_constant_alpha(LTDC_LAYER_2, 255);
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/* Blending factors */
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ltdc_set_blending_factors(LTDC_LAYER_2, LTDC_LxBFCR_BF1_CONST_ALPHA, LTDC_LxBFCR_BF2_CONST_ALPHA);
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/* Framebuffer address */
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ltdc_set_fbuffer_address(LTDC_LAYER_2, (uint32_t)0xC0000000); // XXX SDRAM ADDR!
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/* Configures the color frame buffer pitch in byte */
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ltdc_set_fb_line_length(LTDC_LAYER_2, 2*480, 2*480); /* RGB565 is 2 bytes/pixel */
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/* Configures the frame buffer line number */
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ltdc_set_fb_line_count(LTDC_LAYER_2, 272);
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/* Enable layer 1 */
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ltdc_layer_ctrl_enable(LTDC_LAYER_2, LTDC_LxCR_LAYER_ENABLE);
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/* Sets the Reload type */
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ltdc_reload(LTDC_SRCR_IMR);
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}
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/**
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* @brief LCD Configuration.
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* @note This function Configure tha LTDC peripheral :
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* 1) Configure the Pixel Clock for the LCD
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* 2) Configure the LTDC Timing and Polarity
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* 3) Configure the LTDC Layer 1 :
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* - The frame buffer is located at FLASH memory
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* - The Layer size configuration : 480x272
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* @retval
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* None
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*/
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static void lcd_config(void)
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{
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/* LTDC Initialization */
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ltdc_ctrl_disable(LTDC_GCR_HSPOL_ACTIVE_HIGH); /* Active Low Horizontal Sync */
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ltdc_ctrl_disable(LTDC_GCR_VSPOL_ACTIVE_HIGH); /* Active Low Vertical Sync */
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ltdc_ctrl_disable(LTDC_GCR_DEPOL_ACTIVE_HIGH); /* Active Low Date Enable */
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ltdc_ctrl_disable(LTDC_GCR_PCPOL_ACTIVE_HIGH); /* Active Low Pixel Clock */
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/* Configure the LTDC */
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ltdc_set_tft_sync_timings(RK043FN48H_HSYNC, RK043FN48H_VSYNC,
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RK043FN48H_HBP, RK043FN48H_VBP,
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RK043FN48H_WIDTH, RK043FN48H_HEIGHT,
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RK043FN48H_HFP, RK043FN48H_VFP);
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ltdc_set_background_color(0, 0, 0);
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ltdc_ctrl_enable(LTDC_GCR_LTDC_ENABLE);
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/* Configure the Layer*/
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lcd_config_layer();
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}
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static void lcd_clock(void)
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{
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/* LCD clock configuration */
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/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
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/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
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/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
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/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
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/* Disable PLLSAI */
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RCC_CR &= ~RCC_CR_PLLSAION;
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while((RCC_CR & (RCC_CR_PLLSAIRDY))) {};
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/* N and R are needed,
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* P and Q are not needed for LTDC */
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RCC_PLLSAICFGR &= ~RCC_PLLSAICFGR_PLLSAIN_MASK;
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RCC_PLLSAICFGR |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
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RCC_PLLSAICFGR &= ~RCC_PLLSAICFGR_PLLSAIR_MASK;
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RCC_PLLSAICFGR |= 5 << RCC_PLLSAICFGR_PLLSAIR_SHIFT;
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RCC_DCKCFGR1 &= ~RCC_DCKCFGR1_PLLSAIDIVR_MASK;
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RCC_DCKCFGR1 |= RCC_DCKCFGR1_PLLSAIDIVR_DIVR_4;
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/* Enable PLLSAI */
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RCC_CR |= RCC_CR_PLLSAION;
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while(!(RCC_CR & (RCC_CR_PLLSAIRDY))) {};
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}
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int main(void)
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{
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/* init timers. */
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clock_setup();
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/* init sdram */
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sdram_init();
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/* init LCD */
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lcd_pinmux();
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lcd_clock();
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lcd_config(); /* Configure LCD : Only one layer is used */
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while (1) {
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int x;
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uint16_t * rgb565;
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// write stuff to the framebuffer
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rgb565 = (uint16_t *)SDRAM_BASE_ADDRESS;
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for (x = 0; x < (480*272*2)/2; x++)
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{
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*(rgb565++) = 0x1F; // Blue only
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}
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msleep(200);
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rgb565 = (uint16_t *)SDRAM_BASE_ADDRESS;
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for (x = 0; x < (480*272*2)/2; x++)
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{
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*(rgb565++) = 0x7E0; // Green only
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}
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msleep(200);
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rgb565 = (uint16_t *)SDRAM_BASE_ADDRESS;
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for (x = 0; x < (480*272*2)/2; x++)
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{
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*(rgb565++) = 0xF800; // Red only
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}
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msleep(200);
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}
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}
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‎examples/stm32/f7/stm32f7-discovery/lcd-ram-demo/rk043fn48h.h

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#ifndef __RK043FN48H_H
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#define __RK043FN48H_H
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#include <stdint.h>
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#define RK043FN48H_WIDTH ((uint16_t)480) /* LCD PIXEL WIDTH */
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#define RK043FN48H_HEIGHT ((uint16_t)272) /* LCD PIXEL HEIGHT */
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#define RK043FN48H_HSYNC ((uint16_t)41) /* Horizontal synchronization */
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#define RK043FN48H_HBP ((uint16_t)13) /* Horizontal back porch */
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#define RK043FN48H_HFP ((uint16_t)32) /* Horizontal front porch */
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#define RK043FN48H_VSYNC ((uint16_t)10) /* Vertical synchronization */
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#define RK043FN48H_VBP ((uint16_t)2) /* Vertical back porch */
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#define RK043FN48H_VFP ((uint16_t)2) /* Vertical front porch */
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#define RK043FN48H_FREQUENCY_DIVIDER 5 /* LCD Frequency divider */
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#endif /* __RK043FN48H_H */

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