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| 1 | +/* |
| 2 | + * This file is part of the libopencm3 project. |
| 3 | + * |
| 4 | + * Copyright (C) 2015 Piotr Esden-Tempski <[email protected]> |
| 5 | + * Copyright (C) 2015 Jack Ziesing <[email protected]> |
| 6 | + * |
| 7 | + * This library is free software: you can redistribute it and/or modify |
| 8 | + * it under the terms of the GNU Lesser General Public License as published by |
| 9 | + * the Free Software Foundation, either version 3 of the License, or |
| 10 | + * (at your option) any later version. |
| 11 | + * |
| 12 | + * This library is distributed in the hope that it will be useful, |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + * GNU Lesser General Public License for more details. |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU Lesser General Public License |
| 18 | + * along with this library. If not, see <http://www.gnu.org/licenses/>. |
| 19 | + */ |
| 20 | + |
| 21 | +#include <libopencm3/stm32/rcc.h> |
| 22 | +#include <libopencm3/stm32/gpio.h> |
| 23 | +#include <libopencm3/stm32/timer.h> |
| 24 | +#include <libopencm3/cm3/nvic.h> |
| 25 | +#include <libopencm3/stm32/exti.h> |
| 26 | + |
| 27 | +uint16_t frequency_sequence[18] = { |
| 28 | + 1000, |
| 29 | + 500, |
| 30 | + 1000, |
| 31 | + 500, |
| 32 | + 1000, |
| 33 | + 500, |
| 34 | + 2000, |
| 35 | + 500, |
| 36 | + 2000, |
| 37 | + 500, |
| 38 | + 2000, |
| 39 | + 500, |
| 40 | + 1000, |
| 41 | + 500, |
| 42 | + 1000, |
| 43 | + 500, |
| 44 | + 1000, |
| 45 | + 5000, |
| 46 | +}; |
| 47 | + |
| 48 | +uint16_t frequency_sel = 0; |
| 49 | + |
| 50 | +uint16_t compare_time; |
| 51 | +uint16_t new_time; |
| 52 | +uint16_t frequency; |
| 53 | +int debug = 0; |
| 54 | + |
| 55 | +static void clock_setup(void) |
| 56 | +{ |
| 57 | + rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]); |
| 58 | +} |
| 59 | + |
| 60 | +static void gpio_setup(void) |
| 61 | +{ |
| 62 | + /* Enable GPIOC clock. */ |
| 63 | + rcc_periph_clock_enable(RCC_GPIOD); |
| 64 | + |
| 65 | + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ |
| 66 | + gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, |
| 67 | + GPIO_PUPD_NONE, GPIO12 | GPIO13); |
| 68 | + |
| 69 | + gpio_set(GPIOD, GPIO12); |
| 70 | + gpio_clear(GPIOD, GPIO13); |
| 71 | +} |
| 72 | + |
| 73 | +static void tim_setup(void) |
| 74 | +{ |
| 75 | + /* Enable TIM2 clock. */ |
| 76 | + rcc_periph_clock_enable(RCC_TIM2); |
| 77 | + |
| 78 | + /* Enable TIM2 interrupt. */ |
| 79 | + nvic_enable_irq(NVIC_TIM2_IRQ); |
| 80 | + |
| 81 | + /* Reset TIM2 peripheral. */ |
| 82 | + timer_reset(TIM2); |
| 83 | + |
| 84 | + /* Timer global mode: |
| 85 | + * - No divider |
| 86 | + * - Alignment edge |
| 87 | + * - Direction up |
| 88 | + */ |
| 89 | + timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, |
| 90 | + TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); |
| 91 | + |
| 92 | + /* Reset prescaler value. |
| 93 | + * Running the clock at 5kHz. |
| 94 | + */ |
| 95 | + /* |
| 96 | + * On STM32F4 the timers are not running directly from pure APB1 or |
| 97 | + * APB2 clock busses. The APB1 and APB2 clocks used for timers might |
| 98 | + * be the double of the APB1 and APB2 clocks. This depends on the |
| 99 | + * setting in DCKCFGR register. By default the behaviour is the |
| 100 | + * following: If the Prescaler APBx is greater than 1 the derived timer |
| 101 | + * APBx clocks will be double of the original APBx frequencies. Only if |
| 102 | + * the APBx prescaler is set to 1 the derived timer APBx will equal the |
| 103 | + * original APBx frequencies. |
| 104 | + * |
| 105 | + * In our case here the APB1 is devided by 4 system frequency and APB2 |
| 106 | + * divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will |
| 107 | + * be 2 x APB2. So when we try to calculate the prescaler value we have |
| 108 | + * to use rcc_apb1_freqency * 2!!! |
| 109 | + * |
| 110 | + * For additional information see reference manual for the stm32f4 |
| 111 | + * familiy of chips. Page 204 and 213 |
| 112 | + */ |
| 113 | + timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000)); |
| 114 | + |
| 115 | + /* Enable preload. */ |
| 116 | + timer_disable_preload(TIM2); |
| 117 | + |
| 118 | + /* Continous mode. */ |
| 119 | + timer_continuous_mode(TIM2); |
| 120 | + |
| 121 | + /* Period (36kHz). */ |
| 122 | + timer_set_period(TIM2, 65535); |
| 123 | + |
| 124 | + /* Disable outputs. */ |
| 125 | + timer_disable_oc_output(TIM2, TIM_OC1); |
| 126 | + timer_disable_oc_output(TIM2, TIM_OC2); |
| 127 | + timer_disable_oc_output(TIM2, TIM_OC3); |
| 128 | + timer_disable_oc_output(TIM2, TIM_OC4); |
| 129 | + |
| 130 | + /* -- OC1 configuration -- */ |
| 131 | + |
| 132 | + /* Configure global mode of line 1. */ |
| 133 | + timer_disable_oc_clear(TIM2, TIM_OC1); |
| 134 | + timer_disable_oc_preload(TIM2, TIM_OC1); |
| 135 | + timer_set_oc_slow_mode(TIM2, TIM_OC1); |
| 136 | + timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); |
| 137 | + |
| 138 | + /* Set the capture compare value for OC1. */ |
| 139 | + timer_set_oc_value(TIM2, TIM_OC1, 1000); |
| 140 | + |
| 141 | + /* ---- */ |
| 142 | + |
| 143 | + /* ARR reload enable. */ |
| 144 | + timer_disable_preload(TIM2); |
| 145 | + |
| 146 | + /* Counter enable. */ |
| 147 | + timer_enable_counter(TIM2); |
| 148 | + |
| 149 | + /* Enable commutation interrupt. */ |
| 150 | + timer_enable_irq(TIM2, TIM_DIER_CC1IE); |
| 151 | +} |
| 152 | + |
| 153 | +void tim2_isr(void) |
| 154 | +{ |
| 155 | + if (timer_get_flag(TIM2, TIM_SR_CC1IF)) { |
| 156 | + |
| 157 | + /* Clear compare interrupt flag. */ |
| 158 | + timer_clear_flag(TIM2, TIM_SR_CC1IF); |
| 159 | + |
| 160 | + /* |
| 161 | + * Get current timer value to calculate next |
| 162 | + * compare register value. |
| 163 | + */ |
| 164 | + compare_time = timer_get_counter(TIM2); |
| 165 | + |
| 166 | + /* Calculate and set the next compare value. */ |
| 167 | + frequency = frequency_sequence[frequency_sel++]; |
| 168 | + new_time = compare_time + frequency; |
| 169 | + |
| 170 | + timer_set_oc_value(TIM2, TIM_OC1, new_time); |
| 171 | + if (frequency_sel == 18) |
| 172 | + frequency_sel = 0; |
| 173 | + |
| 174 | + /* Toggle LED to indicate compare event. */ |
| 175 | + gpio_toggle(GPIOD, GPIO12); |
| 176 | + gpio_toggle(GPIOD, GPIO13); |
| 177 | + } |
| 178 | +} |
| 179 | + |
| 180 | +int main(void) |
| 181 | +{ |
| 182 | + clock_setup(); |
| 183 | + gpio_setup(); |
| 184 | + tim_setup(); |
| 185 | + |
| 186 | + while (1) |
| 187 | + __asm("nop"); |
| 188 | + |
| 189 | + return 0; |
| 190 | +} |
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