From 876bc85f20c0f57768d1b84a845668b1f47fc30e Mon Sep 17 00:00:00 2001 From: alexrayne Date: Thu, 9 Mar 2017 00:00:26 +0200 Subject: [PATCH 1/2] !usbd:dwc_otg.h:TXFNUM - this field was misplaceds for stm32f4 + CGINAK !usbd:flush_fifo - now unsures core not access to fifo before flush - according to stm32f4 RM0090 notes. --- include/unicore-mx/common/dwc_otg.h | 1692 +++++++++++++++++++++++++ include/unicore-mx/common/dwc_otg.ucd | 5 +- lib/usbd/backend/usbd_dwc_otg.c | 17 +- 3 files changed, 1710 insertions(+), 4 deletions(-) create mode 100644 include/unicore-mx/common/dwc_otg.h diff --git a/include/unicore-mx/common/dwc_otg.h b/include/unicore-mx/common/dwc_otg.h new file mode 100644 index 00000000..f7583e8b --- /dev/null +++ b/include/unicore-mx/common/dwc_otg.h @@ -0,0 +1,1692 @@ +/* + * This file is part of the unicore-mx project. + * + * Copyright (C) 2010 Gareth McMullin + * Copyright (C) 2016 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * This file is intended to be included by either DWC_OTG_hs.h or DWC_OTG_fs.h + * Contains common definitions of Command and Status Registers (CSR) and their + * bit definitions. + */ + +#ifndef UNICOREMX_COMMON_DWC_OTG_H +#define UNICOREMX_COMMON_DWC_OTG_H + +#include +#include + +#define DWC_OTG_GOTGCTL(base) MMIO32((base) + (0x000)) + +#define DWC_OTG_GOTGCTL_BSVLD_SHIFT (19) +#define DWC_OTG_GOTGCTL_BSVLD (1ul << DWC_OTG_GOTGCTL_BSVLD_SHIFT) + + +#define DWC_OTG_GOTGCTL_ASVLD_SHIFT (18) +#define DWC_OTG_GOTGCTL_ASVLD (1ul << DWC_OTG_GOTGCTL_ASVLD_SHIFT) + + +#define DWC_OTG_GOTGCTL_DBCT_SHIFT (17) +#define DWC_OTG_GOTGCTL_DBCT (1ul << DWC_OTG_GOTGCTL_DBCT_SHIFT) + + +#define DWC_OTG_GOTGCTL_CIDSTS_SHIFT (16) +#define DWC_OTG_GOTGCTL_CIDSTS (1ul << DWC_OTG_GOTGCTL_CIDSTS_SHIFT) + + +#define DWC_OTG_GOTGCTL_DHNPEN_SHIFT (11) +#define DWC_OTG_GOTGCTL_DHNPEN (1 << DWC_OTG_GOTGCTL_DHNPEN_SHIFT) + + +#define DWC_OTG_GOTGCTL_HSHNPEN_SHIFT (10) +#define DWC_OTG_GOTGCTL_HSHNPEN (1 << DWC_OTG_GOTGCTL_HSHNPEN_SHIFT) + + +#define DWC_OTG_GOTGCTL_HNPRQ_SHIFT (9) +#define DWC_OTG_GOTGCTL_HNPRQ (1 << DWC_OTG_GOTGCTL_HNPRQ_SHIFT) + + +#define DWC_OTG_GOTGCTL_HNGSCS_SHIFT (8) +#define DWC_OTG_GOTGCTL_HNGSCS (1 << DWC_OTG_GOTGCTL_HNGSCS_SHIFT) + + +#define DWC_OTG_GOTGCTL_BVALOVAL_SHIFT (7) +#define DWC_OTG_GOTGCTL_BVALOVAL (1 << DWC_OTG_GOTGCTL_BVALOVAL_SHIFT) + + +#define DWC_OTG_GOTGCTL_BVALOEN_SHIFT (6) +#define DWC_OTG_GOTGCTL_BVALOEN (1 << DWC_OTG_GOTGCTL_BVALOEN_SHIFT) + + +#define DWC_OTG_GOTGCTL_AVALOVAL_SHIFT (5) +#define DWC_OTG_GOTGCTL_AVALOVAL (1 << DWC_OTG_GOTGCTL_AVALOVAL_SHIFT) + + +#define DWC_OTG_GOTGCTL_AVALOEN_SHIFT (4) +#define DWC_OTG_GOTGCTL_AVALOEN (1 << DWC_OTG_GOTGCTL_AVALOEN_SHIFT) + + +#define DWC_OTG_GOTGCTL_VBVALOVAL_SHIFT (3) +#define DWC_OTG_GOTGCTL_VBVALOVAL (1 << DWC_OTG_GOTGCTL_VBVALOVAL_SHIFT) + + +#define DWC_OTG_GOTGCTL_VBVALOEN_SHIFT (2) +#define DWC_OTG_GOTGCTL_VBVALOEN (1 << DWC_OTG_GOTGCTL_VBVALOEN_SHIFT) + + +#define DWC_OTG_GOTGCTL_SRQ_SHIFT (1) +#define DWC_OTG_GOTGCTL_SRQ (1 << DWC_OTG_GOTGCTL_SRQ_SHIFT) + + +#define DWC_OTG_GOTGCTL_SRQSCS_SHIFT (0) +#define DWC_OTG_GOTGCTL_SRQSCS (1 << DWC_OTG_GOTGCTL_SRQSCS_SHIFT) + + +#define DWC_OTG_GOTGINT(base) MMIO32((base) + (0x004)) + +// Session end detected. The core sets this bit to indicate that the level of the voltage +// on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V //STM32F4 +#define DWC_OTG_GOTGINT_SEDET_SHIFT (2) +#define DWC_OTG_GOTGINT_SEDET (1 << DWC_OTG_GOTGINT_SEDET_SHIFT) + + +// OTG AHB configuration register +#define DWC_OTG_GAHBCFG(base) MMIO32((base) + (0x008)) + +#define DWC_OTG_GAHBCFG_GINT_SHIFT (0) +#define DWC_OTG_GAHBCFG_GINT (1 << DWC_OTG_GAHBCFG_GINT_SHIFT) + + +#define DWC_OTG_GAHBCFG_TXFELVL_SHIFT (7) +#define DWC_OTG_GAHBCFG_TXFELVL (1 << DWC_OTG_GAHBCFG_TXFELVL_SHIFT) + + +#define DWC_OTG_GAHBCFG_PTXFELVL_SHIFT (8) +#define DWC_OTG_GAHBCFG_PTXFELVL (1 << DWC_OTG_GAHBCFG_PTXFELVL_SHIFT) + + +// OTG USB configuration register +#define DWC_OTG_GUSBCFG(base) MMIO32((base) + (0x00C)) + +#define DWC_OTG_GUSBCFG_CTXPKT_SHIFT (31) +#define DWC_OTG_GUSBCFG_CTXPKT (1ul << DWC_OTG_GUSBCFG_CTXPKT_SHIFT) + + +#define DWC_OTG_GUSBCFG_FDMOD_SHIFT (30) +#define DWC_OTG_GUSBCFG_FDMOD (1ul << DWC_OTG_GUSBCFG_FDMOD_SHIFT) + + +#define DWC_OTG_GUSBCFG_FHMOD_SHIFT (29) +#define DWC_OTG_GUSBCFG_FHMOD (1ul << DWC_OTG_GUSBCFG_FHMOD_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPIIPD_SHIFT (25) +#define DWC_OTG_GUSBCFG_ULPIIPD (1ul << DWC_OTG_GUSBCFG_ULPIIPD_SHIFT) + + +#define DWC_OTG_GUSBCFG_PTCI_SHIFT (24) +#define DWC_OTG_GUSBCFG_PTCI (1ul << DWC_OTG_GUSBCFG_PTCI_SHIFT) + + +#define DWC_OTG_GUSBCFG_PCCI_SHIFT (23) +#define DWC_OTG_GUSBCFG_PCCI (1ul << DWC_OTG_GUSBCFG_PCCI_SHIFT) + + +#define DWC_OTG_GUSBCFG_TSDPS_SHIFT (22) +#define DWC_OTG_GUSBCFG_TSDPS (1ul << DWC_OTG_GUSBCFG_TSDPS_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPIEVBUSI_SHIFT (21) +#define DWC_OTG_GUSBCFG_ULPIEVBUSI (1ul << DWC_OTG_GUSBCFG_ULPIEVBUSI_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPIEVBUSD_SHIFT (20) +#define DWC_OTG_GUSBCFG_ULPIEVBUSD (1ul << DWC_OTG_GUSBCFG_ULPIEVBUSD_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPICSM_SHIFT (19) +#define DWC_OTG_GUSBCFG_ULPICSM (1ul << DWC_OTG_GUSBCFG_ULPICSM_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPIAR_SHIFT (18) +#define DWC_OTG_GUSBCFG_ULPIAR (1ul << DWC_OTG_GUSBCFG_ULPIAR_SHIFT) + + +#define DWC_OTG_GUSBCFG_ULPIFSLS_SHIFT (17) +#define DWC_OTG_GUSBCFG_ULPIFSLS (1ul << DWC_OTG_GUSBCFG_ULPIFSLS_SHIFT) + + +#define DWC_OTG_GUSBCFG_PHYLPCS_SHIFT (15) +#define DWC_OTG_GUSBCFG_PHYLPCS (1 << DWC_OTG_GUSBCFG_PHYLPCS_SHIFT) + + +#define DWC_OTG_GUSBCFG_TRDT_SHIFT (10) +#define DWC_OTG_GUSBCFG_TRDT_MASK (0xf << (DWC_OTG_GUSBCFG_TRDT_SHIFT)) +#define DWC_OTG_GUSBCFG_TRDT(v) (((v) << (DWC_OTG_GUSBCFG_TRDT_SHIFT)) & (DWC_OTG_GUSBCFG_TRDT_MASK)) +#define DWC_OTG_GUSBCFG_TRDT_GET(v) (((v) & (DWC_OTG_GUSBCFG_TRDT_MASK)) >> (DWC_OTG_GUSBCFG_TRDT_SHIFT)) +#define DWC_OTG_GUSBCFG_TRDT_16BIT DWC_OTG_GUSBCFG_TRDT(0x5) +#define DWC_OTG_GUSBCFG_TRDT_8BIT DWC_OTG_GUSBCFG_TRDT(0x9) + + +#define DWC_OTG_GUSBCFG_HNPCAP_SHIFT (9) +#define DWC_OTG_GUSBCFG_HNPCAP (1 << DWC_OTG_GUSBCFG_HNPCAP_SHIFT) + + +#define DWC_OTG_GUSBCFG_SRPCAP_SHIFT (8) +#define DWC_OTG_GUSBCFG_SRPCAP (1 << DWC_OTG_GUSBCFG_SRPCAP_SHIFT) + + +#define DWC_OTG_GUSBCFG_PHYSEL_SHIFT (6) +#define DWC_OTG_GUSBCFG_PHYSEL (1 << DWC_OTG_GUSBCFG_PHYSEL_SHIFT) + + +// OTG reset register +#define DWC_OTG_GRSTCTL(base) MMIO32((base) + (0x010)) + +#define DWC_OTG_GRSTCTL_AHBIDL_SHIFT (31) +#define DWC_OTG_GRSTCTL_AHBIDL (1ul << DWC_OTG_GRSTCTL_AHBIDL_SHIFT) + + +#define DWC_OTG_GRSTCTL_TXFNUM_SHIFT (6) +#define DWC_OTG_GRSTCTL_TXFNUM_MASK (0x1f << (DWC_OTG_GRSTCTL_TXFNUM_SHIFT)) +#define DWC_OTG_GRSTCTL_TXFNUM(v) (((v) << (DWC_OTG_GRSTCTL_TXFNUM_SHIFT)) & (DWC_OTG_GRSTCTL_TXFNUM_MASK)) +#define DWC_OTG_GRSTCTL_TXFNUM_GET(v) (((v) & (DWC_OTG_GRSTCTL_TXFNUM_MASK)) >> (DWC_OTG_GRSTCTL_TXFNUM_SHIFT)) +#define DWC_OTG_GRSTCTL_TXFNUM_ALL DWC_OTG_GRSTCTL_TXFNUM(0x10) + + +#define DWC_OTG_GRSTCTL_TXFFLSH_SHIFT (5) +#define DWC_OTG_GRSTCTL_TXFFLSH (1 << DWC_OTG_GRSTCTL_TXFFLSH_SHIFT) + + +#define DWC_OTG_GRSTCTL_RXFFLSH_SHIFT (4) +#define DWC_OTG_GRSTCTL_RXFFLSH (1 << DWC_OTG_GRSTCTL_RXFFLSH_SHIFT) + + +#define DWC_OTG_GRSTCTL_FCRST_SHIFT (2) +#define DWC_OTG_GRSTCTL_FCRST (1 << DWC_OTG_GRSTCTL_FCRST_SHIFT) + + +#define DWC_OTG_GRSTCTL_HSRST_SHIFT (1) +#define DWC_OTG_GRSTCTL_HSRST (1 << DWC_OTG_GRSTCTL_HSRST_SHIFT) + + +#define DWC_OTG_GRSTCTL_CSRST_SHIFT (0) +#define DWC_OTG_GRSTCTL_CSRST (1 << DWC_OTG_GRSTCTL_CSRST_SHIFT) + + +// OTG interrupt status register +#define DWC_OTG_GINTSTS(base) MMIO32((base) + (0x014)) + +#define DWC_OTG_GINTSTS_WKUPINT_SHIFT (31) +#define DWC_OTG_GINTSTS_WKUPINT (1ul << DWC_OTG_GINTSTS_WKUPINT_SHIFT) + + +#define DWC_OTG_GINTSTS_SRQINT_SHIFT (30) +#define DWC_OTG_GINTSTS_SRQINT (1ul << DWC_OTG_GINTSTS_SRQINT_SHIFT) + + +#define DWC_OTG_GINTSTS_DISCINT_SHIFT (29) +#define DWC_OTG_GINTSTS_DISCINT (1ul << DWC_OTG_GINTSTS_DISCINT_SHIFT) + + +#define DWC_OTG_GINTSTS_CIDSCHG_SHIFT (28) +#define DWC_OTG_GINTSTS_CIDSCHG (1ul << DWC_OTG_GINTSTS_CIDSCHG_SHIFT) + + +#define DWC_OTG_GINTSTS_PTXFE_SHIFT (26) +#define DWC_OTG_GINTSTS_PTXFE (1ul << DWC_OTG_GINTSTS_PTXFE_SHIFT) + + +#define DWC_OTG_GINTSTS_HCINT_SHIFT (25) +#define DWC_OTG_GINTSTS_HCINT (1ul << DWC_OTG_GINTSTS_HCINT_SHIFT) + + +#define DWC_OTG_GINTSTS_HPRTINT_SHIFT (24) +#define DWC_OTG_GINTSTS_HPRTINT (1ul << DWC_OTG_GINTSTS_HPRTINT_SHIFT) + + +#define DWC_OTG_GINTSTS_IPXFR_SHIFT (21) +#define DWC_OTG_GINTSTS_IPXFR (1ul << DWC_OTG_GINTSTS_IPXFR_SHIFT) + + +#define DWC_OTG_GINTSTS_INCOMPISOOUT_SHIFT (21) +#define DWC_OTG_GINTSTS_INCOMPISOOUT (1ul << DWC_OTG_GINTSTS_INCOMPISOOUT_SHIFT) + + +#define DWC_OTG_GINTSTS_IISOIXFR_SHIFT (20) +#define DWC_OTG_GINTSTS_IISOIXFR (1ul << DWC_OTG_GINTSTS_IISOIXFR_SHIFT) + + +#define DWC_OTG_GINTSTS_OEPINT_SHIFT (19) +#define DWC_OTG_GINTSTS_OEPINT (1ul << DWC_OTG_GINTSTS_OEPINT_SHIFT) + + +#define DWC_OTG_GINTSTS_IEPINT_SHIFT (18) +#define DWC_OTG_GINTSTS_IEPINT (1ul << DWC_OTG_GINTSTS_IEPINT_SHIFT) + + +#define DWC_OTG_GINTSTS_EOPF_SHIFT (15) +#define DWC_OTG_GINTSTS_EOPF (1 << DWC_OTG_GINTSTS_EOPF_SHIFT) + + +#define DWC_OTG_GINTSTS_ISOODRP_SHIFT (14) +#define DWC_OTG_GINTSTS_ISOODRP (1 << DWC_OTG_GINTSTS_ISOODRP_SHIFT) + + +#define DWC_OTG_GINTSTS_ENUMDNE_SHIFT (13) +#define DWC_OTG_GINTSTS_ENUMDNE (1 << DWC_OTG_GINTSTS_ENUMDNE_SHIFT) + + +#define DWC_OTG_GINTSTS_USBRST_SHIFT (12) +#define DWC_OTG_GINTSTS_USBRST (1 << DWC_OTG_GINTSTS_USBRST_SHIFT) + + +#define DWC_OTG_GINTSTS_USBSUSP_SHIFT (11) +#define DWC_OTG_GINTSTS_USBSUSP (1 << DWC_OTG_GINTSTS_USBSUSP_SHIFT) + + +#define DWC_OTG_GINTSTS_ESUSP_SHIFT (10) +#define DWC_OTG_GINTSTS_ESUSP (1 << DWC_OTG_GINTSTS_ESUSP_SHIFT) + + +#define DWC_OTG_GINTSTS_GONAKEFF_SHIFT (7) +#define DWC_OTG_GINTSTS_GONAKEFF (1 << DWC_OTG_GINTSTS_GONAKEFF_SHIFT) + + +#define DWC_OTG_GINTSTS_GINAKEFF_SHIFT (6) +#define DWC_OTG_GINTSTS_GINAKEFF (1 << DWC_OTG_GINTSTS_GINAKEFF_SHIFT) + + +#define DWC_OTG_GINTSTS_NPTXFE_SHIFT (5) +#define DWC_OTG_GINTSTS_NPTXFE (1 << DWC_OTG_GINTSTS_NPTXFE_SHIFT) + + +#define DWC_OTG_GINTSTS_RXFLVL_SHIFT (4) +#define DWC_OTG_GINTSTS_RXFLVL (1 << DWC_OTG_GINTSTS_RXFLVL_SHIFT) + + +#define DWC_OTG_GINTSTS_SOF_SHIFT (3) +#define DWC_OTG_GINTSTS_SOF (1 << DWC_OTG_GINTSTS_SOF_SHIFT) + + +#define DWC_OTG_GINTSTS_OTGINT_SHIFT (2) +#define DWC_OTG_GINTSTS_OTGINT (1 << DWC_OTG_GINTSTS_OTGINT_SHIFT) + + +#define DWC_OTG_GINTSTS_MMIS_SHIFT (1) +#define DWC_OTG_GINTSTS_MMIS (1 << DWC_OTG_GINTSTS_MMIS_SHIFT) + + +#define DWC_OTG_GINTSTS_CMOD_SHIFT (0) +#define DWC_OTG_GINTSTS_CMOD (1 << DWC_OTG_GINTSTS_CMOD_SHIFT) + + +// OTG interrupt mask register +#define DWC_OTG_GINTMSK(base) MMIO32((base) + (0x018)) + +#define DWC_OTG_GINTMSK_MMISM_SHIFT (1) +#define DWC_OTG_GINTMSK_MMISM (1 << DWC_OTG_GINTMSK_MMISM_SHIFT) + + +#define DWC_OTG_GINTMSK_OTGINT_SHIFT (2) +#define DWC_OTG_GINTMSK_OTGINT (1 << DWC_OTG_GINTMSK_OTGINT_SHIFT) + + +#define DWC_OTG_GINTMSK_SOFM_SHIFT (3) +#define DWC_OTG_GINTMSK_SOFM (1 << DWC_OTG_GINTMSK_SOFM_SHIFT) + + +#define DWC_OTG_GINTMSK_RXFLVLM_SHIFT (4) +#define DWC_OTG_GINTMSK_RXFLVLM (1 << DWC_OTG_GINTMSK_RXFLVLM_SHIFT) + + +#define DWC_OTG_GINTMSK_NPTXFEM_SHIFT (5) +#define DWC_OTG_GINTMSK_NPTXFEM (1 << DWC_OTG_GINTMSK_NPTXFEM_SHIFT) + + +#define DWC_OTG_GINTMSK_GINAKEFFM_SHIFT (6) +#define DWC_OTG_GINTMSK_GINAKEFFM (1 << DWC_OTG_GINTMSK_GINAKEFFM_SHIFT) + + +#define DWC_OTG_GINTMSK_GONAKEFFM_SHIFT (7) +#define DWC_OTG_GINTMSK_GONAKEFFM (1 << DWC_OTG_GINTMSK_GONAKEFFM_SHIFT) + + +#define DWC_OTG_GINTMSK_ESUSPM_SHIFT (10) +#define DWC_OTG_GINTMSK_ESUSPM (1 << DWC_OTG_GINTMSK_ESUSPM_SHIFT) + + +#define DWC_OTG_GINTMSK_USBSUSPM_SHIFT (11) +#define DWC_OTG_GINTMSK_USBSUSPM (1 << DWC_OTG_GINTMSK_USBSUSPM_SHIFT) + + +#define DWC_OTG_GINTMSK_USBRST_SHIFT (12) +#define DWC_OTG_GINTMSK_USBRST (1 << DWC_OTG_GINTMSK_USBRST_SHIFT) + + +#define DWC_OTG_GINTMSK_ENUMDNEM_SHIFT (13) +#define DWC_OTG_GINTMSK_ENUMDNEM (1 << DWC_OTG_GINTMSK_ENUMDNEM_SHIFT) + + +#define DWC_OTG_GINTMSK_ISOODRPM_SHIFT (14) +#define DWC_OTG_GINTMSK_ISOODRPM (1 << DWC_OTG_GINTMSK_ISOODRPM_SHIFT) + + +#define DWC_OTG_GINTMSK_EOPFM_SHIFT (15) +#define DWC_OTG_GINTMSK_EOPFM (1 << DWC_OTG_GINTMSK_EOPFM_SHIFT) + + +#define DWC_OTG_GINTMSK_EPMISM_SHIFT (17) +#define DWC_OTG_GINTMSK_EPMISM (1ul << DWC_OTG_GINTMSK_EPMISM_SHIFT) + + +#define DWC_OTG_GINTMSK_IEPINT_SHIFT (18) +#define DWC_OTG_GINTMSK_IEPINT (1ul << DWC_OTG_GINTMSK_IEPINT_SHIFT) + + +#define DWC_OTG_GINTMSK_OEPINT_SHIFT (19) +#define DWC_OTG_GINTMSK_OEPINT (1ul << DWC_OTG_GINTMSK_OEPINT_SHIFT) + + +#define DWC_OTG_GINTMSK_IISOIXFRM_SHIFT (20) +#define DWC_OTG_GINTMSK_IISOIXFRM (1ul << DWC_OTG_GINTMSK_IISOIXFRM_SHIFT) + + +#define DWC_OTG_GINTMSK_IISOOXFRM_SHIFT (21) +#define DWC_OTG_GINTMSK_IISOOXFRM (1ul << DWC_OTG_GINTMSK_IISOOXFRM_SHIFT) + + +#define DWC_OTG_GINTMSK_IPXFRM_SHIFT (21) +#define DWC_OTG_GINTMSK_IPXFRM (1ul << DWC_OTG_GINTMSK_IPXFRM_SHIFT) + + +#define DWC_OTG_GINTMSK_PRTIM_SHIFT (24) +#define DWC_OTG_GINTMSK_PRTIM (1ul << DWC_OTG_GINTMSK_PRTIM_SHIFT) + + +#define DWC_OTG_GINTMSK_HCIM_SHIFT (25) +#define DWC_OTG_GINTMSK_HCIM (1ul << DWC_OTG_GINTMSK_HCIM_SHIFT) + + +#define DWC_OTG_GINTMSK_PTXFEM_SHIFT (26) +#define DWC_OTG_GINTMSK_PTXFEM (1ul << DWC_OTG_GINTMSK_PTXFEM_SHIFT) + + +#define DWC_OTG_GINTMSK_CIDSCHGM_SHIFT (28) +#define DWC_OTG_GINTMSK_CIDSCHGM (1ul << DWC_OTG_GINTMSK_CIDSCHGM_SHIFT) + + +#define DWC_OTG_GINTMSK_DISCINT_SHIFT (29) +#define DWC_OTG_GINTMSK_DISCINT (1ul << DWC_OTG_GINTMSK_DISCINT_SHIFT) + + +#define DWC_OTG_GINTMSK_SRQIM_SHIFT (30) +#define DWC_OTG_GINTMSK_SRQIM (1ul << DWC_OTG_GINTMSK_SRQIM_SHIFT) + + +#define DWC_OTG_GINTMSK_WUIM_SHIFT (31) +#define DWC_OTG_GINTMSK_WUIM (1ul << DWC_OTG_GINTMSK_WUIM_SHIFT) + + +#define DWC_OTG_GRXSTSR(base) MMIO32((base) + (0x01C)) + +// OTG Receive Status Pop Register +#define DWC_OTG_GRXSTSP(base) MMIO32((base) + (0x020)) + +#define DWC_OTG_GRXSTSP_FRMNUM_SHIFT (21) +#define DWC_OTG_GRXSTSP_FRMNUM_MASK (0xful << (DWC_OTG_GRXSTSP_FRMNUM_SHIFT)) +#define DWC_OTG_GRXSTSP_FRMNUM(v) (((v) << (DWC_OTG_GRXSTSP_FRMNUM_SHIFT)) & (DWC_OTG_GRXSTSP_FRMNUM_MASK)) +#define DWC_OTG_GRXSTSP_FRMNUM_GET(v) (((v) & (DWC_OTG_GRXSTSP_FRMNUM_MASK)) >> (DWC_OTG_GRXSTSP_FRMNUM_SHIFT)) + + +#define DWC_OTG_GRXSTSP_PKTSTS_SHIFT (17) +#define DWC_OTG_GRXSTSP_PKTSTS_MASK (0xful << (DWC_OTG_GRXSTSP_PKTSTS_SHIFT)) +#define DWC_OTG_GRXSTSP_PKTSTS(v) (((v) << (DWC_OTG_GRXSTSP_PKTSTS_SHIFT)) & (DWC_OTG_GRXSTSP_PKTSTS_MASK)) +#define DWC_OTG_GRXSTSP_PKTSTS_GET(v) (((v) & (DWC_OTG_GRXSTSP_PKTSTS_MASK)) >> (DWC_OTG_GRXSTSP_PKTSTS_SHIFT)) +#define DWC_OTG_GRXSTSP_PKTSTS_GOUTNAK DWC_OTG_GRXSTSP_PKTSTS(0x1) +#define DWC_OTG_GRXSTSP_PKTSTS_OUT DWC_OTG_GRXSTSP_PKTSTS(0x2) +#define DWC_OTG_GRXSTSP_PKTSTS_IN DWC_OTG_GRXSTSP_PKTSTS(0x2) +#define DWC_OTG_GRXSTSP_PKTSTS_OUT_COMP DWC_OTG_GRXSTSP_PKTSTS(0x3) +#define DWC_OTG_GRXSTSP_PKTSTS_IN_COMP DWC_OTG_GRXSTSP_PKTSTS(0x3) +#define DWC_OTG_GRXSTSP_PKTSTS_SETUP_COMP DWC_OTG_GRXSTSP_PKTSTS(0x4) +#define DWC_OTG_GRXSTSP_PKTSTS_DTERR DWC_OTG_GRXSTSP_PKTSTS(0x5) +#define DWC_OTG_GRXSTSP_PKTSTS_SETUP DWC_OTG_GRXSTSP_PKTSTS(0x6) +#define DWC_OTG_GRXSTSP_PKTSTS_CHH DWC_OTG_GRXSTSP_PKTSTS(0x7) + + +#define DWC_OTG_GRXSTSP_DPID_SHIFT (15) +#define DWC_OTG_GRXSTSP_DPID_MASK (0x3 << (DWC_OTG_GRXSTSP_DPID_SHIFT)) +#define DWC_OTG_GRXSTSP_DPID(v) (((v) << (DWC_OTG_GRXSTSP_DPID_SHIFT)) & (DWC_OTG_GRXSTSP_DPID_MASK)) +#define DWC_OTG_GRXSTSP_DPID_GET(v) (((v) & (DWC_OTG_GRXSTSP_DPID_MASK)) >> (DWC_OTG_GRXSTSP_DPID_SHIFT)) +#define DWC_OTG_GRXSTSP_DPID_DATA0 DWC_OTG_GRXSTSP_DPID(0x0) +#define DWC_OTG_GRXSTSP_DPID_DATA1 DWC_OTG_GRXSTSP_DPID(0x2) +#define DWC_OTG_GRXSTSP_DPID_DATA2 DWC_OTG_GRXSTSP_DPID(0x1) +#define DWC_OTG_GRXSTSP_DPID_MDATA DWC_OTG_GRXSTSP_DPID(0x3) + + +#define DWC_OTG_GRXSTSP_BCNT_SHIFT (4) +#define DWC_OTG_GRXSTSP_BCNT_MASK (0x7ff << (DWC_OTG_GRXSTSP_BCNT_SHIFT)) +#define DWC_OTG_GRXSTSP_BCNT(v) (((v) << (DWC_OTG_GRXSTSP_BCNT_SHIFT)) & (DWC_OTG_GRXSTSP_BCNT_MASK)) +#define DWC_OTG_GRXSTSP_BCNT_GET(v) (((v) & (DWC_OTG_GRXSTSP_BCNT_MASK)) >> (DWC_OTG_GRXSTSP_BCNT_SHIFT)) + + +#define DWC_OTG_GRXSTSP_EPNUM_SHIFT (0) +#define DWC_OTG_GRXSTSP_EPNUM_MASK (0xf << (DWC_OTG_GRXSTSP_EPNUM_SHIFT)) +#define DWC_OTG_GRXSTSP_EPNUM(v) (((v) << (DWC_OTG_GRXSTSP_EPNUM_SHIFT)) & (DWC_OTG_GRXSTSP_EPNUM_MASK)) +#define DWC_OTG_GRXSTSP_EPNUM_GET(v) (((v) & (DWC_OTG_GRXSTSP_EPNUM_MASK)) >> (DWC_OTG_GRXSTSP_EPNUM_SHIFT)) + + +#define DWC_OTG_GRXFSIZ(base) MMIO32((base) + (0x024)) + +#define DWC_OTG_GNPTXFSIZ(base) MMIO32((base) + (0x028)) + +#define DWC_OTG_GNPTXFSIZ_NPTXFD_SHIFT (16) +#define DWC_OTG_GNPTXFSIZ_NPTXFD_MASK (0xfffful << (DWC_OTG_GNPTXFSIZ_NPTXFD_SHIFT)) +#define DWC_OTG_GNPTXFSIZ_NPTXFD(v) (((v) << (DWC_OTG_GNPTXFSIZ_NPTXFD_SHIFT)) & (DWC_OTG_GNPTXFSIZ_NPTXFD_MASK)) +#define DWC_OTG_GNPTXFSIZ_NPTXFD_GET(v) (((v) & (DWC_OTG_GNPTXFSIZ_NPTXFD_MASK)) >> (DWC_OTG_GNPTXFSIZ_NPTXFD_SHIFT)) + + +#define DWC_OTG_GNPTXFSIZ_NPTXFSA_SHIFT (0) +#define DWC_OTG_GNPTXFSIZ_NPTXFSA_MASK (0xffff << (DWC_OTG_GNPTXFSIZ_NPTXFSA_SHIFT)) +#define DWC_OTG_GNPTXFSIZ_NPTXFSA(v) (((v) << (DWC_OTG_GNPTXFSIZ_NPTXFSA_SHIFT)) & (DWC_OTG_GNPTXFSIZ_NPTXFSA_MASK)) +#define DWC_OTG_GNPTXFSIZ_NPTXFSA_GET(v) (((v) & (DWC_OTG_GNPTXFSIZ_NPTXFSA_MASK)) >> (DWC_OTG_GNPTXFSIZ_NPTXFSA_SHIFT)) + + +#define DWC_OTG_DIEP0TXF(base) MMIO32((base) + (0x028)) + +#define DWC_OTG_DIEP0TXF_TX0FD_SHIFT (16) +#define DWC_OTG_DIEP0TXF_TX0FD_MASK (0xfffful << (DWC_OTG_DIEP0TXF_TX0FD_SHIFT)) +#define DWC_OTG_DIEP0TXF_TX0FD(v) (((v) << (DWC_OTG_DIEP0TXF_TX0FD_SHIFT)) & (DWC_OTG_DIEP0TXF_TX0FD_MASK)) +#define DWC_OTG_DIEP0TXF_TX0FD_GET(v) (((v) & (DWC_OTG_DIEP0TXF_TX0FD_MASK)) >> (DWC_OTG_DIEP0TXF_TX0FD_SHIFT)) + + +#define DWC_OTG_DIEP0TXF_TX0FSA_SHIFT (0) +#define DWC_OTG_DIEP0TXF_TX0FSA_MASK (0xffff << (DWC_OTG_DIEP0TXF_TX0FSA_SHIFT)) +#define DWC_OTG_DIEP0TXF_TX0FSA(v) (((v) << (DWC_OTG_DIEP0TXF_TX0FSA_SHIFT)) & (DWC_OTG_DIEP0TXF_TX0FSA_MASK)) +#define DWC_OTG_DIEP0TXF_TX0FSA_GET(v) (((v) & (DWC_OTG_DIEP0TXF_TX0FSA_MASK)) >> (DWC_OTG_DIEP0TXF_TX0FSA_SHIFT)) + + +#define DWC_OTG_GNPTXSTS(base) MMIO32((base) + (0x02C)) + +#define DWC_OTG_GGPIO(base) MMIO32((base) + (0x038)) + +#define DWC_OTG_GUID(base) MMIO32((base) + (0x03C)) + +#define DWC_OTG_GSNPSID(base) MMIO32((base) + (0x040)) + +#define DWC_OTG_GHWCFG1(base) MMIO32((base) + (0x044)) + +#define DWC_OTG_GHWCFG1_EPDIR_SHIFT(i) (0 + ((i*2))) +#define DWC_OTG_GHWCFG1_EPDIR_MASK(i) (0x3ul << (DWC_OTG_GHWCFG1_EPDIR_SHIFT(i))) +#define DWC_OTG_GHWCFG1_EPDIR(v, i) (((v) << (DWC_OTG_GHWCFG1_EPDIR_SHIFT(i))) & (DWC_OTG_GHWCFG1_EPDIR_MASK(i))) +#define DWC_OTG_GHWCFG1_EPDIR_GET(v, i) (((v) & (DWC_OTG_GHWCFG1_EPDIR_MASK(i))) >> (DWC_OTG_GHWCFG1_EPDIR_SHIFT(i))) +#define DWC_OTG_GHWCFG1_EPDIR_BIDIR(i) DWC_OTG_GHWCFG1_EPDIR(0x0, i) +#define DWC_OTG_GHWCFG1_EPDIR_IN(i) DWC_OTG_GHWCFG1_EPDIR(0x1, i) +#define DWC_OTG_GHWCFG1_EPDIR_OUT(i) DWC_OTG_GHWCFG1_EPDIR(0x2, i) + + +#define DWC_OTG_GHWCFG2(base) MMIO32((base) + (0x048)) + +// Number of device endpoints +#define DWC_OTG_GHWCFG2_NUMHSTCHNL_SHIFT (14) +#define DWC_OTG_GHWCFG2_NUMHSTCHNL_MASK (0xf << (DWC_OTG_GHWCFG2_NUMHSTCHNL_SHIFT)) +#define DWC_OTG_GHWCFG2_NUMHSTCHNL(v) (((v) << (DWC_OTG_GHWCFG2_NUMHSTCHNL_SHIFT)) & (DWC_OTG_GHWCFG2_NUMHSTCHNL_MASK)) +#define DWC_OTG_GHWCFG2_NUMHSTCHNL_GET(v) (((v) & (DWC_OTG_GHWCFG2_NUMHSTCHNL_MASK)) >> (DWC_OTG_GHWCFG2_NUMHSTCHNL_SHIFT)) + + +#define DWC_OTG_GHWCFG2_NUMDEVEPS_SHIFT (10) +#define DWC_OTG_GHWCFG2_NUMDEVEPS_MASK (0xf << (DWC_OTG_GHWCFG2_NUMDEVEPS_SHIFT)) +#define DWC_OTG_GHWCFG2_NUMDEVEPS(v) (((v) << (DWC_OTG_GHWCFG2_NUMDEVEPS_SHIFT)) & (DWC_OTG_GHWCFG2_NUMDEVEPS_MASK)) +#define DWC_OTG_GHWCFG2_NUMDEVEPS_GET(v) (((v) & (DWC_OTG_GHWCFG2_NUMDEVEPS_MASK)) >> (DWC_OTG_GHWCFG2_NUMDEVEPS_SHIFT)) + + +#define DWC_OTG_GHWCFG3(base) MMIO32((base) + (0x04C)) + +// DFIFO Depth +#define DWC_OTG_GHWCFG3_DFIFODEPTH_SHIFT (16) +#define DWC_OTG_GHWCFG3_DFIFODEPTH_MASK (0xfffful << (DWC_OTG_GHWCFG3_DFIFODEPTH_SHIFT)) +#define DWC_OTG_GHWCFG3_DFIFODEPTH(v) (((v) << (DWC_OTG_GHWCFG3_DFIFODEPTH_SHIFT)) & (DWC_OTG_GHWCFG3_DFIFODEPTH_MASK)) +#define DWC_OTG_GHWCFG3_DFIFODEPTH_GET(v) (((v) & (DWC_OTG_GHWCFG3_DFIFODEPTH_MASK)) >> (DWC_OTG_GHWCFG3_DFIFODEPTH_SHIFT)) + + +// Width of Packet Size Counters (Actual = value + 4) +#define DWC_OTG_GHWCFG3_PKTSIZEWIDTH_SHIFT (4) +#define DWC_OTG_GHWCFG3_PKTSIZEWIDTH_MASK (0x7 << (DWC_OTG_GHWCFG3_PKTSIZEWIDTH_SHIFT)) +#define DWC_OTG_GHWCFG3_PKTSIZEWIDTH(v) (((v) << (DWC_OTG_GHWCFG3_PKTSIZEWIDTH_SHIFT)) & (DWC_OTG_GHWCFG3_PKTSIZEWIDTH_MASK)) +#define DWC_OTG_GHWCFG3_PKTSIZEWIDTH_GET(v) (((v) & (DWC_OTG_GHWCFG3_PKTSIZEWIDTH_MASK)) >> (DWC_OTG_GHWCFG3_PKTSIZEWIDTH_SHIFT)) + + +// Width of Transfer Size Counters (Actual = value + 11) +#define DWC_OTG_GHWCFG3_XFERSIZEWIDTH_SHIFT (0) +#define DWC_OTG_GHWCFG3_XFERSIZEWIDTH_MASK (0xf << (DWC_OTG_GHWCFG3_XFERSIZEWIDTH_SHIFT)) +#define DWC_OTG_GHWCFG3_XFERSIZEWIDTH(v) (((v) << (DWC_OTG_GHWCFG3_XFERSIZEWIDTH_SHIFT)) & (DWC_OTG_GHWCFG3_XFERSIZEWIDTH_MASK)) +#define DWC_OTG_GHWCFG3_XFERSIZEWIDTH_GET(v) (((v) & (DWC_OTG_GHWCFG3_XFERSIZEWIDTH_MASK)) >> (DWC_OTG_GHWCFG3_XFERSIZEWIDTH_SHIFT)) + + +#define DWC_OTG_GHWCFG4(base) MMIO32((base) + (0x050)) + +// OTG Host periodic transmit FIFO size register +#define DWC_OTG_HPTXFSIZ(base) MMIO32((base) + (0x100)) + +#define DWC_OTG_HPTXFSIZ_PTXFD_SHIFT (16) +#define DWC_OTG_HPTXFSIZ_PTXFD_MASK (0xfffful << (DWC_OTG_HPTXFSIZ_PTXFD_SHIFT)) +#define DWC_OTG_HPTXFSIZ_PTXFD(v) (((v) << (DWC_OTG_HPTXFSIZ_PTXFD_SHIFT)) & (DWC_OTG_HPTXFSIZ_PTXFD_MASK)) +#define DWC_OTG_HPTXFSIZ_PTXFD_GET(v) (((v) & (DWC_OTG_HPTXFSIZ_PTXFD_MASK)) >> (DWC_OTG_HPTXFSIZ_PTXFD_SHIFT)) + + +#define DWC_OTG_HPTXFSIZ_PTXSA_SHIFT (0) +#define DWC_OTG_HPTXFSIZ_PTXSA_MASK (0xffff << (DWC_OTG_HPTXFSIZ_PTXSA_SHIFT)) +#define DWC_OTG_HPTXFSIZ_PTXSA(v) (((v) << (DWC_OTG_HPTXFSIZ_PTXSA_SHIFT)) & (DWC_OTG_HPTXFSIZ_PTXSA_MASK)) +#define DWC_OTG_HPTXFSIZ_PTXSA_GET(v) (((v) & (DWC_OTG_HPTXFSIZ_PTXSA_MASK)) >> (DWC_OTG_HPTXFSIZ_PTXSA_SHIFT)) + + +#define DWC_OTG_DIEPxTXF(base, x) MMIO32((base) + (0x104) + (4*((x)-1))) + +#define DWC_OTG_DIEPTXF_INEPTXFD_SHIFT (16) +#define DWC_OTG_DIEPTXF_INEPTXFD_MASK (0xfffful << (DWC_OTG_DIEPTXF_INEPTXFD_SHIFT)) +#define DWC_OTG_DIEPTXF_INEPTXFD(v) (((v) << (DWC_OTG_DIEPTXF_INEPTXFD_SHIFT)) & (DWC_OTG_DIEPTXF_INEPTXFD_MASK)) +#define DWC_OTG_DIEPTXF_INEPTXFD_GET(v) (((v) & (DWC_OTG_DIEPTXF_INEPTXFD_MASK)) >> (DWC_OTG_DIEPTXF_INEPTXFD_SHIFT)) + + +#define DWC_OTG_DIEPTXF_INEPTXSA_SHIFT (0) +#define DWC_OTG_DIEPTXF_INEPTXSA_MASK (0xffff << (DWC_OTG_DIEPTXF_INEPTXSA_SHIFT)) +#define DWC_OTG_DIEPTXF_INEPTXSA(v) (((v) << (DWC_OTG_DIEPTXF_INEPTXSA_SHIFT)) & (DWC_OTG_DIEPTXF_INEPTXSA_MASK)) +#define DWC_OTG_DIEPTXF_INEPTXSA_GET(v) (((v) & (DWC_OTG_DIEPTXF_INEPTXSA_MASK)) >> (DWC_OTG_DIEPTXF_INEPTXSA_SHIFT)) + + +// Host-mode Control and Status Registers +// OTG Host Configuration Register +#define DWC_OTG_HCFG(base) MMIO32((base) + (0x400)) + +#define DWC_OTG_HCFG_FSLSS_SHIFT (2) +#define DWC_OTG_HCFG_FSLSS (1 << DWC_OTG_HCFG_FSLSS_SHIFT) + + +#define DWC_OTG_HCFG_FSLSPCS_SHIFT (0) +#define DWC_OTG_HCFG_FSLSPCS_MASK (0x3 << (DWC_OTG_HCFG_FSLSPCS_SHIFT)) +#define DWC_OTG_HCFG_FSLSPCS(v) (((v) << (DWC_OTG_HCFG_FSLSPCS_SHIFT)) & (DWC_OTG_HCFG_FSLSPCS_MASK)) +#define DWC_OTG_HCFG_FSLSPCS_GET(v) (((v) & (DWC_OTG_HCFG_FSLSPCS_MASK)) >> (DWC_OTG_HCFG_FSLSPCS_SHIFT)) +#define DWC_OTG_HCFG_FSLSPCS_48MHz DWC_OTG_HCFG_FSLSPCS(0x1) +#define DWC_OTG_HCFG_FSLSPCS_6MHz DWC_OTG_HCFG_FSLSPCS(0x2) + + +#define DWC_OTG_HFIR(base) MMIO32((base) + (0x404)) + +#define DWC_OTG_HFIR_FRIVL_SHIFT (0) +#define DWC_OTG_HFIR_FRIVL_MASK (0xffff << (DWC_OTG_HFIR_FRIVL_SHIFT)) +#define DWC_OTG_HFIR_FRIVL(v) (((v) << (DWC_OTG_HFIR_FRIVL_SHIFT)) & (DWC_OTG_HFIR_FRIVL_MASK)) +#define DWC_OTG_HFIR_FRIVL_GET(v) (((v) & (DWC_OTG_HFIR_FRIVL_MASK)) >> (DWC_OTG_HFIR_FRIVL_SHIFT)) + + +// OTG Host frame number/frame time remaining register +#define DWC_OTG_HFNUM(base) MMIO32((base) + (0x408)) + +#define DWC_OTG_HFNUM_FTREM_SHIFT (16) +#define DWC_OTG_HFNUM_FTREM_MASK (0xfffful << (DWC_OTG_HFNUM_FTREM_SHIFT)) +#define DWC_OTG_HFNUM_FTREM(v) (((v) << (DWC_OTG_HFNUM_FTREM_SHIFT)) & (DWC_OTG_HFNUM_FTREM_MASK)) +#define DWC_OTG_HFNUM_FTREM_GET(v) (((v) & (DWC_OTG_HFNUM_FTREM_MASK)) >> (DWC_OTG_HFNUM_FTREM_SHIFT)) + + +#define DWC_OTG_HFNUM_FRNUM_SHIFT (0) +#define DWC_OTG_HFNUM_FRNUM_MASK (0xffff << (DWC_OTG_HFNUM_FRNUM_SHIFT)) +#define DWC_OTG_HFNUM_FRNUM(v) (((v) << (DWC_OTG_HFNUM_FRNUM_SHIFT)) & (DWC_OTG_HFNUM_FRNUM_MASK)) +#define DWC_OTG_HFNUM_FRNUM_GET(v) (((v) & (DWC_OTG_HFNUM_FRNUM_MASK)) >> (DWC_OTG_HFNUM_FRNUM_SHIFT)) + + +// OTG Host periodic transmit FIFO/queue status +#define DWC_OTG_HPTXSTS(base) MMIO32((base) + (0x410)) + +#define DWC_OTG_HPTXSTS_PTXQTOP_SHIFT (24) +#define DWC_OTG_HPTXSTS_PTXQTOP_MASK (0xfful << (DWC_OTG_HPTXSTS_PTXQTOP_SHIFT)) +#define DWC_OTG_HPTXSTS_PTXQTOP(v) (((v) << (DWC_OTG_HPTXSTS_PTXQTOP_SHIFT)) & (DWC_OTG_HPTXSTS_PTXQTOP_MASK)) +#define DWC_OTG_HPTXSTS_PTXQTOP_GET(v) (((v) & (DWC_OTG_HPTXSTS_PTXQTOP_MASK)) >> (DWC_OTG_HPTXSTS_PTXQTOP_SHIFT)) + + + +#define DWC_OTG_HPTXSTS_PTXQTOP_ODDFRM (1<<31) +#define DWC_OTG_HPTXSTS_PTXQTOP_EVENFRM (0<<31) +#define DWC_OTG_HPTXSTS_PTXQTOP_CHANNEL_NUMBER_MASK (0xf<<27) +#define DWC_OTG_HPTXSTS_PTXQTOP_ENDPOINT_NUMBER_MASK (0xf<<27) +#define DWC_OTG_HPTXSTS_PTXQTOP_TYPE_INOUT (0x00<<25) +#define DWC_OTG_HPTXSTS_PTXQTOP_TYPE_ZEROLENGTH (0x01<<25) +#define DWC_OTG_HPTXSTS_PTXQTOP_TYPE_DISABLECMD (0x11<<25) +#define DWC_OTG_HPTXSTS_PTXQTOP_TERMINATE (1<<24) + +#define DWC_OTG_HPTXSTS_PTXQSAV_SHIFT (16) +#define DWC_OTG_HPTXSTS_PTXQSAV_MASK (0xfful << (DWC_OTG_HPTXSTS_PTXQSAV_SHIFT)) +#define DWC_OTG_HPTXSTS_PTXQSAV(v) (((v) << (DWC_OTG_HPTXSTS_PTXQSAV_SHIFT)) & (DWC_OTG_HPTXSTS_PTXQSAV_MASK)) +#define DWC_OTG_HPTXSTS_PTXQSAV_GET(v) (((v) & (DWC_OTG_HPTXSTS_PTXQSAV_MASK)) >> (DWC_OTG_HPTXSTS_PTXQSAV_SHIFT)) + + +#define DWC_OTG_HPTXSTS_PTXFSAVL_SHIFT (0) +#define DWC_OTG_HPTXSTS_PTXFSAVL_MASK (0xffff << (DWC_OTG_HPTXSTS_PTXFSAVL_SHIFT)) +#define DWC_OTG_HPTXSTS_PTXFSAVL(v) (((v) << (DWC_OTG_HPTXSTS_PTXFSAVL_SHIFT)) & (DWC_OTG_HPTXSTS_PTXFSAVL_MASK)) +#define DWC_OTG_HPTXSTS_PTXFSAVL_GET(v) (((v) & (DWC_OTG_HPTXSTS_PTXFSAVL_MASK)) >> (DWC_OTG_HPTXSTS_PTXFSAVL_SHIFT)) + + +// OTG Host all channels interrupt register +#define DWC_OTG_HAINT(base) MMIO32((base) + (0x414)) + +// OTG Host all channels interrupt mask register +#define DWC_OTG_HAINTMSK(base) MMIO32((base) + (0x418)) + +// OTG Host port control and status register +#define DWC_OTG_HPRT(base) MMIO32((base) + (0x440)) + +#define DWC_OTG_HPRT_PSPD_SHIFT (17) +#define DWC_OTG_HPRT_PSPD_MASK (0x3ul << (DWC_OTG_HPRT_PSPD_SHIFT)) +#define DWC_OTG_HPRT_PSPD(v) (((v) << (DWC_OTG_HPRT_PSPD_SHIFT)) & (DWC_OTG_HPRT_PSPD_MASK)) +#define DWC_OTG_HPRT_PSPD_GET(v) (((v) & (DWC_OTG_HPRT_PSPD_MASK)) >> (DWC_OTG_HPRT_PSPD_SHIFT)) +#define DWC_OTG_HPRT_PSPD_HIGH DWC_OTG_HPRT_PSPD(0x0) +#define DWC_OTG_HPRT_PSPD_FULL DWC_OTG_HPRT_PSPD(0x1) +#define DWC_OTG_HPRT_PSPD_LOW DWC_OTG_HPRT_PSPD(0x2) + + +#define DWC_OTG_HPRT_PTCTL_SHIFT (13) +#define DWC_OTG_HPRT_PTCTL_MASK (0xf << (DWC_OTG_HPRT_PTCTL_SHIFT)) +#define DWC_OTG_HPRT_PTCTL(v) (((v) << (DWC_OTG_HPRT_PTCTL_SHIFT)) & (DWC_OTG_HPRT_PTCTL_MASK)) +#define DWC_OTG_HPRT_PTCTL_GET(v) (((v) & (DWC_OTG_HPRT_PTCTL_MASK)) >> (DWC_OTG_HPRT_PTCTL_SHIFT)) +#define DWC_OTG_HPRT_PTCTL_DISABLED DWC_OTG_HPRT_PTCTL(0x0) +#define DWC_OTG_HPRT_PTCTL_J DWC_OTG_HPRT_PTCTL(0x1) +#define DWC_OTG_HPRT_PTCTL_K DWC_OTG_HPRT_PTCTL(0x2) +#define DWC_OTG_HPRT_PTCTL_SE0_NAK DWC_OTG_HPRT_PTCTL(0x3) +#define DWC_OTG_HPRT_PTCTL_PACKET DWC_OTG_HPRT_PTCTL(0x4) +#define DWC_OTG_HPRT_PTCTL_FORCE_ENABLE DWC_OTG_HPRT_PTCTL(0x4) + + +#define DWC_OTG_HPRT_PPWR_SHIFT (12) +#define DWC_OTG_HPRT_PPWR (1 << DWC_OTG_HPRT_PPWR_SHIFT) + + +#define DWC_OTG_HPRT_PLSTS_DM_SHIFT (11) +#define DWC_OTG_HPRT_PLSTS_DM (1 << DWC_OTG_HPRT_PLSTS_DM_SHIFT) + + +#define DWC_OTG_HPRT_PLSTS_DP_SHIFT (10) +#define DWC_OTG_HPRT_PLSTS_DP (1 << DWC_OTG_HPRT_PLSTS_DP_SHIFT) + + +#define DWC_OTG_HPRT_PRST_SHIFT (8) +#define DWC_OTG_HPRT_PRST (1 << DWC_OTG_HPRT_PRST_SHIFT) + + +#define DWC_OTG_HPRT_PSUSP_SHIFT (7) +#define DWC_OTG_HPRT_PSUSP (1 << DWC_OTG_HPRT_PSUSP_SHIFT) + + +#define DWC_OTG_HPRT_PRES_SHIFT (6) +#define DWC_OTG_HPRT_PRES (1 << DWC_OTG_HPRT_PRES_SHIFT) + + +#define DWC_OTG_HPRT_POCCHNG_SHIFT (5) +#define DWC_OTG_HPRT_POCCHNG (1 << DWC_OTG_HPRT_POCCHNG_SHIFT) + + +#define DWC_OTG_HPRT_POCA_SHIFT (4) +#define DWC_OTG_HPRT_POCA (1 << DWC_OTG_HPRT_POCA_SHIFT) + + +#define DWC_OTG_HPRT_PENCHNG_SHIFT (3) +#define DWC_OTG_HPRT_PENCHNG (1 << DWC_OTG_HPRT_PENCHNG_SHIFT) + + +#define DWC_OTG_HPRT_PENA_SHIFT (2) +#define DWC_OTG_HPRT_PENA (1 << DWC_OTG_HPRT_PENA_SHIFT) + + +#define DWC_OTG_HPRT_PCDET_SHIFT (1) +#define DWC_OTG_HPRT_PCDET (1 << DWC_OTG_HPRT_PCDET_SHIFT) + + +#define DWC_OTG_HPRT_PCSTS_SHIFT (0) +#define DWC_OTG_HPRT_PCSTS (1 << DWC_OTG_HPRT_PCSTS_SHIFT) + + +// OTG Host channel-x characteristics register +#define DWC_OTG_HCxCHAR(base, x) MMIO32((base) + (0x500) + (0x20*(x))) + +#define DWC_OTG_HCCHAR_CHENA_SHIFT (31) +#define DWC_OTG_HCCHAR_CHENA (1ul << DWC_OTG_HCCHAR_CHENA_SHIFT) + + +#define DWC_OTG_HCCHAR_CHDIS_SHIFT (30) +#define DWC_OTG_HCCHAR_CHDIS (1ul << DWC_OTG_HCCHAR_CHDIS_SHIFT) + + +#define DWC_OTG_HCCHAR_ODDFRM_SHIFT (29) +#define DWC_OTG_HCCHAR_ODDFRM (1ul << DWC_OTG_HCCHAR_ODDFRM_SHIFT) + + +#define DWC_OTG_HCCHAR_DAD_SHIFT (22) +#define DWC_OTG_HCCHAR_DAD_MASK (0x7ful << (DWC_OTG_HCCHAR_DAD_SHIFT)) +#define DWC_OTG_HCCHAR_DAD(v) (((v) << (DWC_OTG_HCCHAR_DAD_SHIFT)) & (DWC_OTG_HCCHAR_DAD_MASK)) +#define DWC_OTG_HCCHAR_DAD_GET(v) (((v) & (DWC_OTG_HCCHAR_DAD_MASK)) >> (DWC_OTG_HCCHAR_DAD_SHIFT)) + + +#define DWC_OTG_HCCHAR_MCNT_SHIFT (20) +#define DWC_OTG_HCCHAR_MCNT_MASK (0x3ul << (DWC_OTG_HCCHAR_MCNT_SHIFT)) +#define DWC_OTG_HCCHAR_MCNT(v) (((v) << (DWC_OTG_HCCHAR_MCNT_SHIFT)) & (DWC_OTG_HCCHAR_MCNT_MASK)) +#define DWC_OTG_HCCHAR_MCNT_GET(v) (((v) & (DWC_OTG_HCCHAR_MCNT_MASK)) >> (DWC_OTG_HCCHAR_MCNT_SHIFT)) +#define DWC_OTG_HCCHAR_MCNT_1 DWC_OTG_HCCHAR_MCNT(0x1) +#define DWC_OTG_HCCHAR_MCNT_2 DWC_OTG_HCCHAR_MCNT(0x2) +#define DWC_OTG_HCCHAR_MCNT_3 DWC_OTG_HCCHAR_MCNT(0x3) + + +#define DWC_OTG_HCCHAR_EPTYP_SHIFT (18) +#define DWC_OTG_HCCHAR_EPTYP_MASK (0x3ul << (DWC_OTG_HCCHAR_EPTYP_SHIFT)) +#define DWC_OTG_HCCHAR_EPTYP(v) (((v) << (DWC_OTG_HCCHAR_EPTYP_SHIFT)) & (DWC_OTG_HCCHAR_EPTYP_MASK)) +#define DWC_OTG_HCCHAR_EPTYP_GET(v) (((v) & (DWC_OTG_HCCHAR_EPTYP_MASK)) >> (DWC_OTG_HCCHAR_EPTYP_SHIFT)) +#define DWC_OTG_HCCHAR_EPTYP_CONTROL DWC_OTG_HCCHAR_EPTYP(0x0) +#define DWC_OTG_HCCHAR_EPTYP_ISOCHRONOUS DWC_OTG_HCCHAR_EPTYP(0x1) +#define DWC_OTG_HCCHAR_EPTYP_BULK DWC_OTG_HCCHAR_EPTYP(0x2) +#define DWC_OTG_HCCHAR_EPTYP_INTERRUPT DWC_OTG_HCCHAR_EPTYP(0x3) + + +#define DWC_OTG_HCCHAR_LSDEV_SHIFT (17) +#define DWC_OTG_HCCHAR_LSDEV (1ul << DWC_OTG_HCCHAR_LSDEV_SHIFT) + + +#define DWC_OTG_HCCHAR_EPDIR_SHIFT (15) +#define DWC_OTG_HCCHAR_EPDIR_MASK (0x1 << (DWC_OTG_HCCHAR_EPDIR_SHIFT)) +#define DWC_OTG_HCCHAR_EPDIR(v) (((v) << (DWC_OTG_HCCHAR_EPDIR_SHIFT)) & (DWC_OTG_HCCHAR_EPDIR_MASK)) +#define DWC_OTG_HCCHAR_EPDIR_GET(v) (((v) & (DWC_OTG_HCCHAR_EPDIR_MASK)) >> (DWC_OTG_HCCHAR_EPDIR_SHIFT)) +#define DWC_OTG_HCCHAR_EPDIR_OUT DWC_OTG_HCCHAR_EPDIR(0x0) +#define DWC_OTG_HCCHAR_EPDIR_IN DWC_OTG_HCCHAR_EPDIR(0x1) + + +#define DWC_OTG_HCCHAR_EPNUM_SHIFT (11) +#define DWC_OTG_HCCHAR_EPNUM_MASK (0xf << (DWC_OTG_HCCHAR_EPNUM_SHIFT)) +#define DWC_OTG_HCCHAR_EPNUM(v) (((v) << (DWC_OTG_HCCHAR_EPNUM_SHIFT)) & (DWC_OTG_HCCHAR_EPNUM_MASK)) +#define DWC_OTG_HCCHAR_EPNUM_GET(v) (((v) & (DWC_OTG_HCCHAR_EPNUM_MASK)) >> (DWC_OTG_HCCHAR_EPNUM_SHIFT)) + + +#define DWC_OTG_HCCHAR_MPSIZ_SHIFT (0) +#define DWC_OTG_HCCHAR_MPSIZ_MASK (0x7ff << (DWC_OTG_HCCHAR_MPSIZ_SHIFT)) +#define DWC_OTG_HCCHAR_MPSIZ(v) (((v) << (DWC_OTG_HCCHAR_MPSIZ_SHIFT)) & (DWC_OTG_HCCHAR_MPSIZ_MASK)) +#define DWC_OTG_HCCHAR_MPSIZ_GET(v) (((v) & (DWC_OTG_HCCHAR_MPSIZ_MASK)) >> (DWC_OTG_HCCHAR_MPSIZ_SHIFT)) + + +// OTG host channel-x split control register +#define DWC_OTG_HCxSPLT(base, x) MMIO32((base) + (0x504) + (0x20*(x))) + +#define DWC_OTG_HCSPLT_SPLITEN_SHIFT (31) +#define DWC_OTG_HCSPLT_SPLITEN (1ul << DWC_OTG_HCSPLT_SPLITEN_SHIFT) + + +#define DWC_OTG_HCSPLT_XACTPOS_SHIFT (14) +#define DWC_OTG_HCSPLT_XACTPOS_MASK (0x3 << (DWC_OTG_HCSPLT_XACTPOS_SHIFT)) +#define DWC_OTG_HCSPLT_XACTPOS(v) (((v) << (DWC_OTG_HCSPLT_XACTPOS_SHIFT)) & (DWC_OTG_HCSPLT_XACTPOS_MASK)) +#define DWC_OTG_HCSPLT_XACTPOS_GET(v) (((v) & (DWC_OTG_HCSPLT_XACTPOS_MASK)) >> (DWC_OTG_HCSPLT_XACTPOS_SHIFT)) +#define DWC_OTG_HCSPLT_XACTPOS_ALL DWC_OTG_HCSPLT_XACTPOS(0x3) +#define DWC_OTG_HCSPLT_XACTPOS_BEGIN DWC_OTG_HCSPLT_XACTPOS(0x2) +#define DWC_OTG_HCSPLT_XACTPOS_MID DWC_OTG_HCSPLT_XACTPOS(0x0) +#define DWC_OTG_HCSPLT_XACTPOS_END DWC_OTG_HCSPLT_XACTPOS(0x1) + + +#define DWC_OTG_HCSPLT_HUBADDR_SHIFT (7) +#define DWC_OTG_HCSPLT_HUBADDR_MASK (0x7f << (DWC_OTG_HCSPLT_HUBADDR_SHIFT)) +#define DWC_OTG_HCSPLT_HUBADDR(v) (((v) << (DWC_OTG_HCSPLT_HUBADDR_SHIFT)) & (DWC_OTG_HCSPLT_HUBADDR_MASK)) +#define DWC_OTG_HCSPLT_HUBADDR_GET(v) (((v) & (DWC_OTG_HCSPLT_HUBADDR_MASK)) >> (DWC_OTG_HCSPLT_HUBADDR_SHIFT)) + + +#define DWC_OTG_HCSPLT_PORTADDR_SHIFT (0) +#define DWC_OTG_HCSPLT_PORTADDR_MASK (0x7f << (DWC_OTG_HCSPLT_PORTADDR_SHIFT)) +#define DWC_OTG_HCSPLT_PORTADDR(v) (((v) << (DWC_OTG_HCSPLT_PORTADDR_SHIFT)) & (DWC_OTG_HCSPLT_PORTADDR_MASK)) +#define DWC_OTG_HCSPLT_PORTADDR_GET(v) (((v) & (DWC_OTG_HCSPLT_PORTADDR_MASK)) >> (DWC_OTG_HCSPLT_PORTADDR_SHIFT)) + + +// OTG Host channel-x interrupt register +#define DWC_OTG_HCxINT(base, x) MMIO32((base) + (0x508) + (0x20*(x))) + +#define DWC_OTG_HCINT_DTERR_SHIFT (10) +#define DWC_OTG_HCINT_DTERR (1 << DWC_OTG_HCINT_DTERR_SHIFT) + + +#define DWC_OTG_HCINT_FRMOR_SHIFT (9) +#define DWC_OTG_HCINT_FRMOR (1 << DWC_OTG_HCINT_FRMOR_SHIFT) + + +#define DWC_OTG_HCINT_BBERR_SHIFT (8) +#define DWC_OTG_HCINT_BBERR (1 << DWC_OTG_HCINT_BBERR_SHIFT) + + +#define DWC_OTG_HCINT_TXERR_SHIFT (7) +#define DWC_OTG_HCINT_TXERR (1 << DWC_OTG_HCINT_TXERR_SHIFT) + + +// Note: NYET: Only in High Speed +#define DWC_OTG_HCINT_NYET_SHIFT (6) +#define DWC_OTG_HCINT_NYET (1 << DWC_OTG_HCINT_NYET_SHIFT) + + +#define DWC_OTG_HCINT_ACK_SHIFT (5) +#define DWC_OTG_HCINT_ACK (1 << DWC_OTG_HCINT_ACK_SHIFT) + + +#define DWC_OTG_HCINT_NAK_SHIFT (4) +#define DWC_OTG_HCINT_NAK (1 << DWC_OTG_HCINT_NAK_SHIFT) + + +#define DWC_OTG_HCINT_STALL_SHIFT (3) +#define DWC_OTG_HCINT_STALL (1 << DWC_OTG_HCINT_STALL_SHIFT) + + +// Note: AHBERR: Only in High Speed +#define DWC_OTG_HCINT_AHBERR_SHIFT (2) +#define DWC_OTG_HCINT_AHBERR (1 << DWC_OTG_HCINT_AHBERR_SHIFT) + + +#define DWC_OTG_HCINT_CHH_SHIFT (1) +#define DWC_OTG_HCINT_CHH (1 << DWC_OTG_HCINT_CHH_SHIFT) + + +#define DWC_OTG_HCINT_XFRC_SHIFT (0) +#define DWC_OTG_HCINT_XFRC (1 << DWC_OTG_HCINT_XFRC_SHIFT) + + +// OTG Host channel-x interrupt mask register +#define DWC_OTG_HCxINTMSK(base, x) MMIO32((base) + (0x50C) + (0x20*(x))) + +#define DWC_OTG_HCINTMSK_DTERRM_SHIFT (10) +#define DWC_OTG_HCINTMSK_DTERRM (1 << DWC_OTG_HCINTMSK_DTERRM_SHIFT) + + +#define DWC_OTG_HCINTMSK_FRMORM_SHIFT (9) +#define DWC_OTG_HCINTMSK_FRMORM (1 << DWC_OTG_HCINTMSK_FRMORM_SHIFT) + + +#define DWC_OTG_HCINTMSK_BBERRM_SHIFT (8) +#define DWC_OTG_HCINTMSK_BBERRM (1 << DWC_OTG_HCINTMSK_BBERRM_SHIFT) + + +#define DWC_OTG_HCINTMSK_TXERRM7_SHIFT (9) +#define DWC_OTG_HCINTMSK_TXERRM7 (1 << DWC_OTG_HCINTMSK_TXERRM7_SHIFT) + + +// Note: NYET: Only in High Speed +#define DWC_OTG_HCINTMSK_NYET_SHIFT (6) +#define DWC_OTG_HCINTMSK_NYET (1 << DWC_OTG_HCINTMSK_NYET_SHIFT) + + +#define DWC_OTG_HCINTMSK_ACKM_SHIFT (5) +#define DWC_OTG_HCINTMSK_ACKM (1 << DWC_OTG_HCINTMSK_ACKM_SHIFT) + + +#define DWC_OTG_HCINTMSK_NAKM_SHIFT (4) +#define DWC_OTG_HCINTMSK_NAKM (1 << DWC_OTG_HCINTMSK_NAKM_SHIFT) + + +#define DWC_OTG_HCINTMSK_STALLM_SHIFT (3) +#define DWC_OTG_HCINTMSK_STALLM (1 << DWC_OTG_HCINTMSK_STALLM_SHIFT) + + +// Note: AHBERR: Only in High Speed +#define DWC_OTG_HCINTMSK_AHBERR_SHIFT (2) +#define DWC_OTG_HCINTMSK_AHBERR (1 << DWC_OTG_HCINTMSK_AHBERR_SHIFT) + + +#define DWC_OTG_HCINTMSK_CHHM_SHIFT (1) +#define DWC_OTG_HCINTMSK_CHHM (1 << DWC_OTG_HCINTMSK_CHHM_SHIFT) + + +#define DWC_OTG_HCINTMSK_XFRCM_SHIFT (0) +#define DWC_OTG_HCINTMSK_XFRCM (1 << DWC_OTG_HCINTMSK_XFRCM_SHIFT) + + +// OTG Host channel-x transfer size register +#define DWC_OTG_HCxTSIZ(base, x) MMIO32((base) + (0x510) + (0x20*(x))) + +#define DWC_OTG_HCTSIZ_DOPING_SHIFT (31) +#define DWC_OTG_HCTSIZ_DOPING (1ul << DWC_OTG_HCTSIZ_DOPING_SHIFT) + + +#define DWC_OTG_HCTSIZ_DPID_SHIFT (29) +#define DWC_OTG_HCTSIZ_DPID_MASK (0x3ul << (DWC_OTG_HCTSIZ_DPID_SHIFT)) +#define DWC_OTG_HCTSIZ_DPID(v) (((v) << (DWC_OTG_HCTSIZ_DPID_SHIFT)) & (DWC_OTG_HCTSIZ_DPID_MASK)) +#define DWC_OTG_HCTSIZ_DPID_GET(v) (((v) & (DWC_OTG_HCTSIZ_DPID_MASK)) >> (DWC_OTG_HCTSIZ_DPID_SHIFT)) +#define DWC_OTG_HCTSIZ_DPID_DATA0 DWC_OTG_HCTSIZ_DPID(0x0) +#define DWC_OTG_HCTSIZ_DPID_DATA1 DWC_OTG_HCTSIZ_DPID(0x2) +#define DWC_OTG_HCTSIZ_DPID_DATA2 DWC_OTG_HCTSIZ_DPID(0x1) +#define DWC_OTG_HCTSIZ_DPID_MDATA DWC_OTG_HCTSIZ_DPID(0x3) + + +#define DWC_OTG_HCTSIZ_PKTCNT_SHIFT (19) +#define DWC_OTG_HCTSIZ_PKTCNT_MASK (0x3fful << (DWC_OTG_HCTSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_HCTSIZ_PKTCNT(v) (((v) << (DWC_OTG_HCTSIZ_PKTCNT_SHIFT)) & (DWC_OTG_HCTSIZ_PKTCNT_MASK)) +#define DWC_OTG_HCTSIZ_PKTCNT_GET(v) (((v) & (DWC_OTG_HCTSIZ_PKTCNT_MASK)) >> (DWC_OTG_HCTSIZ_PKTCNT_SHIFT)) + + +#define DWC_OTG_HCTSIZ_XFRSIZ_SHIFT (0) +#define DWC_OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << (DWC_OTG_HCTSIZ_XFRSIZ_SHIFT)) +#define DWC_OTG_HCTSIZ_XFRSIZ(v) (((v) << (DWC_OTG_HCTSIZ_XFRSIZ_SHIFT)) & (DWC_OTG_HCTSIZ_XFRSIZ_MASK)) +#define DWC_OTG_HCTSIZ_XFRSIZ_GET(v) (((v) & (DWC_OTG_HCTSIZ_XFRSIZ_MASK)) >> (DWC_OTG_HCTSIZ_XFRSIZ_SHIFT)) + + +#define DWC_OTG_HCxDMA(base, x) MMIO32((base) + (0x514) + (0x20*(x))) + +#define DWC_OTG_DCFG(base) MMIO32((base) + (0x800)) + +#define DWC_OTG_DCFG_DAD_SHIFT (4) +#define DWC_OTG_DCFG_DAD_MASK (0x7f << (DWC_OTG_DCFG_DAD_SHIFT)) +#define DWC_OTG_DCFG_DAD(v) (((v) << (DWC_OTG_DCFG_DAD_SHIFT)) & (DWC_OTG_DCFG_DAD_MASK)) +#define DWC_OTG_DCFG_DAD_GET(v) (((v) & (DWC_OTG_DCFG_DAD_MASK)) >> (DWC_OTG_DCFG_DAD_SHIFT)) + + +#define DWC_OTG_DCFG_NZLSOHSK_SHIFT (3) +#define DWC_OTG_DCFG_NZLSOHSK (1 << DWC_OTG_DCFG_NZLSOHSK_SHIFT) + + +#define DWC_OTG_DCFG_DSPD_SHIFT (0) +#define DWC_OTG_DCFG_DSPD_MASK (0x3 << (DWC_OTG_DCFG_DSPD_SHIFT)) +#define DWC_OTG_DCFG_DSPD(v) (((v) << (DWC_OTG_DCFG_DSPD_SHIFT)) & (DWC_OTG_DCFG_DSPD_MASK)) +#define DWC_OTG_DCFG_DSPD_GET(v) (((v) & (DWC_OTG_DCFG_DSPD_MASK)) >> (DWC_OTG_DCFG_DSPD_SHIFT)) +#define DWC_OTG_DCFG_DSPD_HIGH DWC_OTG_DCFG_DSPD(0x0) +#define DWC_OTG_DCFG_DSPD_FULL_2_0 DWC_OTG_DCFG_DSPD(0x1) +#define DWC_OTG_DCFG_DSPD_LOW DWC_OTG_DCFG_DSPD(0x2) +#define DWC_OTG_DCFG_DSPD_FULL_1_1 DWC_OTG_DCFG_DSPD(0x3) + + +#define DWC_OTG_DCTL(base) MMIO32((base) + (0x804)) + +#define DWC_OTG_DCTL_POPRGDNE_SHIFT (11) +#define DWC_OTG_DCTL_POPRGDNE (1 << DWC_OTG_DCTL_POPRGDNE_SHIFT) + + +#define DWC_OTG_DCTL_CGONAK_SHIFT (10) +#define DWC_OTG_DCTL_CGONAK (1 << DWC_OTG_DCTL_CGONAK_SHIFT) + + +#define DWC_OTG_DCTL_SGONAK_SHIFT (9) +#define DWC_OTG_DCTL_SGONAK (1 << DWC_OTG_DCTL_SGONAK_SHIFT) + + +#define DWC_OTG_DCTL_CGINAK_SHIFT (8) +#define DWC_OTG_DCTL_CGINAK (1 << DWC_OTG_DCTL_CGINAK_SHIFT) + + +#define DWC_OTG_DCTL_SGINAK_SHIFT (7) +#define DWC_OTG_DCTL_SGINAK (1 << DWC_OTG_DCTL_SGINAK_SHIFT) + + +#define DWC_OTG_DCTL_TCTL_SHIFT (4) +#define DWC_OTG_DCTL_TCTL_MASK (0x7 << (DWC_OTG_DCTL_TCTL_SHIFT)) +#define DWC_OTG_DCTL_TCTL(v) (((v) << (DWC_OTG_DCTL_TCTL_SHIFT)) & (DWC_OTG_DCTL_TCTL_MASK)) +#define DWC_OTG_DCTL_TCTL_GET(v) (((v) & (DWC_OTG_DCTL_TCTL_MASK)) >> (DWC_OTG_DCTL_TCTL_SHIFT)) + + +#define DWC_OTG_DCTL_GONSTS_SHIFT (3) +#define DWC_OTG_DCTL_GONSTS (1 << DWC_OTG_DCTL_GONSTS_SHIFT) + + +#define DWC_OTG_DCTL_GINSTS_SHIFT (2) +#define DWC_OTG_DCTL_GINSTS (1 << DWC_OTG_DCTL_GINSTS_SHIFT) + + +#define DWC_OTG_DCTL_SDIS_SHIFT (1) +#define DWC_OTG_DCTL_SDIS (1 << DWC_OTG_DCTL_SDIS_SHIFT) + + +#define DWC_OTG_DCTL_RWUSIG_SHIFT (0) +#define DWC_OTG_DCTL_RWUSIG (1 << DWC_OTG_DCTL_RWUSIG_SHIFT) + + +// Device mode status register +#define DWC_OTG_DSTS(base) MMIO32((base) + (0x808)) + +#define DWC_OTG_DSTS_FNSOF_SHIFT (8) +#define DWC_OTG_DSTS_FNSOF_MASK (0x3fff << (DWC_OTG_DSTS_FNSOF_SHIFT)) +#define DWC_OTG_DSTS_FNSOF(v) (((v) << (DWC_OTG_DSTS_FNSOF_SHIFT)) & (DWC_OTG_DSTS_FNSOF_MASK)) +#define DWC_OTG_DSTS_FNSOF_GET(v) (((v) & (DWC_OTG_DSTS_FNSOF_MASK)) >> (DWC_OTG_DSTS_FNSOF_SHIFT)) + + +#define DWC_OTG_DSTS_EERR_SHIFT (3) +#define DWC_OTG_DSTS_EERR (1 << DWC_OTG_DSTS_EERR_SHIFT) + + +#define DWC_OTG_DSTS_ENUMSPD_SHIFT (1) +#define DWC_OTG_DSTS_ENUMSPD_MASK (0x3 << (DWC_OTG_DSTS_ENUMSPD_SHIFT)) +#define DWC_OTG_DSTS_ENUMSPD(v) (((v) << (DWC_OTG_DSTS_ENUMSPD_SHIFT)) & (DWC_OTG_DSTS_ENUMSPD_MASK)) +#define DWC_OTG_DSTS_ENUMSPD_GET(v) (((v) & (DWC_OTG_DSTS_ENUMSPD_MASK)) >> (DWC_OTG_DSTS_ENUMSPD_SHIFT)) +#define DWC_OTG_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ DWC_OTG_DSTS_ENUMSPD(0x0) +#define DWC_OTG_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ DWC_OTG_DSTS_ENUMSPD(0x1) +#define DWC_OTG_DSTS_ENUMSPD_LS_PHY_6MHZ DWC_OTG_DSTS_ENUMSPD(0x2) +#define DWC_OTG_DSTS_ENUMSPD_FS_PHY_48MHZ DWC_OTG_DSTS_ENUMSPD(0x3) + + +#define DWC_OTG_DSTS_SUSPSTS_SHIFT (0) +#define DWC_OTG_DSTS_SUSPSTS (1 << DWC_OTG_DSTS_SUSPSTS_SHIFT) + + +// OTG Device IN Endpoint Common Interrupt Mask Register +#define DWC_OTG_DIEPMSK(base) MMIO32((base) + (0x810)) + +#define DWC_OTG_DIEPMSK_BIM_SHIFT (9) +#define DWC_OTG_DIEPMSK_BIM (1 << DWC_OTG_DIEPMSK_BIM_SHIFT) + + +#define DWC_OTG_DIEPMSK_TXFURM_SHIFT (8) +#define DWC_OTG_DIEPMSK_TXFURM (1 << DWC_OTG_DIEPMSK_TXFURM_SHIFT) + + +#define DWC_OTG_DIEPMSK_INEPNEM_SHIFT (6) +#define DWC_OTG_DIEPMSK_INEPNEM (1 << DWC_OTG_DIEPMSK_INEPNEM_SHIFT) + + +#define DWC_OTG_DIEPMSK_INEPNMM_SHIFT (5) +#define DWC_OTG_DIEPMSK_INEPNMM (1 << DWC_OTG_DIEPMSK_INEPNMM_SHIFT) + + +#define DWC_OTG_DIEPMSK_ITTXFEM_SHIFT (4) +#define DWC_OTG_DIEPMSK_ITTXFEM (1 << DWC_OTG_DIEPMSK_ITTXFEM_SHIFT) + + +#define DWC_OTG_DIEPMSK_TOM_SHIFT (3) +#define DWC_OTG_DIEPMSK_TOM (1 << DWC_OTG_DIEPMSK_TOM_SHIFT) + + +#define DWC_OTG_DIEPMSK_EPDM_SHIFT (1) +#define DWC_OTG_DIEPMSK_EPDM (1 << DWC_OTG_DIEPMSK_EPDM_SHIFT) + + +#define DWC_OTG_DIEPMSK_XFRCM_SHIFT (0) +#define DWC_OTG_DIEPMSK_XFRCM (1 << DWC_OTG_DIEPMSK_XFRCM_SHIFT) + + +// OTG Device OUT Endpoint Common Interrupt Mask Register +#define DWC_OTG_DOEPMSK(base) MMIO32((base) + (0x814)) + +#define DWC_OTG_DOEPMSK_BBLERR_SHIFT (12) +#define DWC_OTG_DOEPMSK_BBLERR (1 << DWC_OTG_DOEPMSK_BBLERR_SHIFT) + + +#define DWC_OTG_DOEPMSK_BOIM_SHIFT (9) +#define DWC_OTG_DOEPMSK_BOIM (1 << DWC_OTG_DOEPMSK_BOIM_SHIFT) + + +#define DWC_OTG_DOEPMSK_OPEM_SHIFT (8) +#define DWC_OTG_DOEPMSK_OPEM (1 << DWC_OTG_DOEPMSK_OPEM_SHIFT) + + +#define DWC_OTG_DOEPMSK_B2BSTUP_SHIFT (6) +#define DWC_OTG_DOEPMSK_B2BSTUP (1 << DWC_OTG_DOEPMSK_B2BSTUP_SHIFT) + + +#define DWC_OTG_DOEPMSK_OTEPDM_SHIFT (4) +#define DWC_OTG_DOEPMSK_OTEPDM (1 << DWC_OTG_DOEPMSK_OTEPDM_SHIFT) + + +#define DWC_OTG_DOEPMSK_STUPM_SHIFT (3) +#define DWC_OTG_DOEPMSK_STUPM (1 << DWC_OTG_DOEPMSK_STUPM_SHIFT) + + +#define DWC_OTG_DOEPMSK_EPDM_SHIFT (1) +#define DWC_OTG_DOEPMSK_EPDM (1 << DWC_OTG_DOEPMSK_EPDM_SHIFT) + + +#define DWC_OTG_DOEPMSK_XFRCM_SHIFT (0) +#define DWC_OTG_DOEPMSK_XFRCM (1 << DWC_OTG_DOEPMSK_XFRCM_SHIFT) + + +#define DWC_OTG_DAINT(base) MMIO32((base) + (0x818)) + +#define DWC_OTG_DAINT_OEPINT_SHIFT(x) (16 + ((x))) +#define DWC_OTG_DAINT_OEPINT(x) (1ul << DWC_OTG_DAINT_OEPINT_SHIFT(x)) + + +#define DWC_OTG_DAINT_IEPINT_SHIFT(x) (0 + ((x))) +#define DWC_OTG_DAINT_IEPINT(x) (1ul << DWC_OTG_DAINT_IEPINT_SHIFT(x)) + + +#define DWC_OTG_DAINTMSK(base) MMIO32((base) + (0x81C)) + +#define DWC_OTG_DAINTMSK_OEPM_SHIFT(x) (16 + ((x))) +#define DWC_OTG_DAINTMSK_OEPM(x) (1ul << DWC_OTG_DAINTMSK_OEPM_SHIFT(x)) + + +#define DWC_OTG_DAINTMSK_IEPM_SHIFT(x) (0 + ((x))) +#define DWC_OTG_DAINTMSK_IEPM(x) (1ul << DWC_OTG_DAINTMSK_IEPM_SHIFT(x)) + + +#define DWC_OTG_DVBUSDIS(base) MMIO32((base) + (0x828)) + +#define DWC_OTG_DVBUSPULSE(base) MMIO32((base) + (0x82C)) + +#define DWC_OTG_DIEPEMPMSK(base) MMIO32((base) + (0x834)) + +#define DWC_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT(x) (0 + ((x))) +#define DWC_OTG_DIEPEMPMSK_INEPTXFEM(x) (1ul << DWC_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT(x)) + + +#define DWC_OTG_DEACHINT(base) MMIO32((base) + (0x838)) + +#define DWC_OTG_DEACHINT_OEP1INT_SHIFT (17) +#define DWC_OTG_DEACHINT_OEP1INT (1ul << DWC_OTG_DEACHINT_OEP1INT_SHIFT) + + +#define DWC_OTG_DEACHINT_IEP1INT_SHIFT (1) +#define DWC_OTG_DEACHINT_IEP1INT (1 << DWC_OTG_DEACHINT_IEP1INT_SHIFT) + + +#define DWC_OTG_DEACHINTMSK(base) MMIO32((base) + (0x83C)) + +// OTG device each in endpoint-1 interrupt register +#define DWC_OTG_DIEPEACHMSK1(base) MMIO32((base) + (0x844)) + +#define DWC_OTG_DIEPEACHMSK1_NAKM_SHIFT (13) +#define DWC_OTG_DIEPEACHMSK1_NAKM (1 << DWC_OTG_DIEPEACHMSK1_NAKM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_BIM_SHIFT (9) +#define DWC_OTG_DIEPEACHMSK1_BIM (1 << DWC_OTG_DIEPEACHMSK1_BIM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_TXFURM_SHIFT (8) +#define DWC_OTG_DIEPEACHMSK1_TXFURM (1 << DWC_OTG_DIEPEACHMSK1_TXFURM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_INEPNEM_SHIFT (5) +#define DWC_OTG_DIEPEACHMSK1_INEPNEM (1 << DWC_OTG_DIEPEACHMSK1_INEPNEM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT (4) +#define DWC_OTG_DIEPEACHMSK1_ITTXFEMSK (1 << DWC_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_TOM_SHIFT (3) +#define DWC_OTG_DIEPEACHMSK1_TOM (1 << DWC_OTG_DIEPEACHMSK1_TOM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_EPDM_SHIFT (1) +#define DWC_OTG_DIEPEACHMSK1_EPDM (1 << DWC_OTG_DIEPEACHMSK1_EPDM_SHIFT) + + +#define DWC_OTG_DIEPEACHMSK1_XFRCM0_SHIFT (2) +#define DWC_OTG_DIEPEACHMSK1_XFRCM0 (1 << DWC_OTG_DIEPEACHMSK1_XFRCM0_SHIFT) + + +// OTG device each OUT endpoint-1 interrupt register +#define DWC_OTG_DOEPEACHMSK1(base) MMIO32((base) + (0x884)) + +#define DWC_OTG_DOEPEACHMSK1_NYETM_SHIFT (14) +#define DWC_OTG_DOEPEACHMSK1_NYETM (1 << DWC_OTG_DOEPEACHMSK1_NYETM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_NAKM_SHIFT (13) +#define DWC_OTG_DOEPEACHMSK1_NAKM (1 << DWC_OTG_DOEPEACHMSK1_NAKM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_BERRM_SHIFT (12) +#define DWC_OTG_DOEPEACHMSK1_BERRM (1 << DWC_OTG_DOEPEACHMSK1_BERRM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_BIM_SHIFT (9) +#define DWC_OTG_DOEPEACHMSK1_BIM (1 << DWC_OTG_DOEPEACHMSK1_BIM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_OPEM_SHIFT (8) +#define DWC_OTG_DOEPEACHMSK1_OPEM (1 << DWC_OTG_DOEPEACHMSK1_OPEM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_AHBERRM_SHIFT (2) +#define DWC_OTG_DOEPEACHMSK1_AHBERRM (1 << DWC_OTG_DOEPEACHMSK1_AHBERRM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_EPDM_SHIFT (1) +#define DWC_OTG_DOEPEACHMSK1_EPDM (1 << DWC_OTG_DOEPEACHMSK1_EPDM_SHIFT) + + +#define DWC_OTG_DOEPEACHMSK1_XFRCM_SHIFT (0) +#define DWC_OTG_DOEPEACHMSK1_XFRCM (1 << DWC_OTG_DOEPEACHMSK1_XFRCM_SHIFT) + + +// OTG Device Control IN Endpoint x Control Register +#define DWC_OTG_DIEPxCTL(base, x) MMIO32((base) + (0x900) + (0x20*(x))) + +#define DWC_OTG_DIEPCTL_EPENA_SHIFT (31) +#define DWC_OTG_DIEPCTL_EPENA (1ul << DWC_OTG_DIEPCTL_EPENA_SHIFT) + + +#define DWC_OTG_DIEPCTL_EPDIS_SHIFT (30) +#define DWC_OTG_DIEPCTL_EPDIS (1ul << DWC_OTG_DIEPCTL_EPDIS_SHIFT) + + +#define DWC_OTG_DIEPCTL_SD1PID_SHIFT (29) +#define DWC_OTG_DIEPCTL_SD1PID (1ul << DWC_OTG_DIEPCTL_SD1PID_SHIFT) + + +#define DWC_OTG_DIEPCTL_SODDFRM_SHIFT (29) +#define DWC_OTG_DIEPCTL_SODDFRM (1ul << DWC_OTG_DIEPCTL_SODDFRM_SHIFT) + + +#define DWC_OTG_DIEPCTL_SD0PID_SHIFT (28) +#define DWC_OTG_DIEPCTL_SD0PID (1ul << DWC_OTG_DIEPCTL_SD0PID_SHIFT) + + +#define DWC_OTG_DIEPCTL_SEVNFRM_SHIFT (28) +#define DWC_OTG_DIEPCTL_SEVNFRM (1ul << DWC_OTG_DIEPCTL_SEVNFRM_SHIFT) + + +#define DWC_OTG_DIEPCTL_SNAK_SHIFT (27) +#define DWC_OTG_DIEPCTL_SNAK (1ul << DWC_OTG_DIEPCTL_SNAK_SHIFT) + + +#define DWC_OTG_DIEPCTL_CNAK_SHIFT (26) +#define DWC_OTG_DIEPCTL_CNAK (1ul << DWC_OTG_DIEPCTL_CNAK_SHIFT) + + +#define DWC_OTG_DIEPCTL_TXFNUM_SHIFT (22) +#define DWC_OTG_DIEPCTL_TXFNUM_MASK (0xful << (DWC_OTG_DIEPCTL_TXFNUM_SHIFT)) +#define DWC_OTG_DIEPCTL_TXFNUM(v) (((v) << (DWC_OTG_DIEPCTL_TXFNUM_SHIFT)) & (DWC_OTG_DIEPCTL_TXFNUM_MASK)) +#define DWC_OTG_DIEPCTL_TXFNUM_GET(v) (((v) & (DWC_OTG_DIEPCTL_TXFNUM_MASK)) >> (DWC_OTG_DIEPCTL_TXFNUM_SHIFT)) + + +#define DWC_OTG_DIEPCTL_STALL_SHIFT (21) +#define DWC_OTG_DIEPCTL_STALL (1ul << DWC_OTG_DIEPCTL_STALL_SHIFT) + + +#define DWC_OTG_DIEPCTL_EPTYP_SHIFT (18) +#define DWC_OTG_DIEPCTL_EPTYP_MASK (0x3ul << (DWC_OTG_DIEPCTL_EPTYP_SHIFT)) +#define DWC_OTG_DIEPCTL_EPTYP(v) (((v) << (DWC_OTG_DIEPCTL_EPTYP_SHIFT)) & (DWC_OTG_DIEPCTL_EPTYP_MASK)) +#define DWC_OTG_DIEPCTL_EPTYP_GET(v) (((v) & (DWC_OTG_DIEPCTL_EPTYP_MASK)) >> (DWC_OTG_DIEPCTL_EPTYP_SHIFT)) +#define DWC_OTG_DIEPCTL_EPTYP_CONTROL DWC_OTG_DIEPCTL_EPTYP(0x0) +#define DWC_OTG_DIEPCTL_EPTYP_ISOCHRONOUS DWC_OTG_DIEPCTL_EPTYP(0x1) +#define DWC_OTG_DIEPCTL_EPTYP_BULK DWC_OTG_DIEPCTL_EPTYP(0x2) +#define DWC_OTG_DIEPCTL_EPTYP_INTERRUPT DWC_OTG_DIEPCTL_EPTYP(0x3) + + +#define DWC_OTG_DIEPCTL_NAKSTS_SHIFT (17) +#define DWC_OTG_DIEPCTL_NAKSTS (1ul << DWC_OTG_DIEPCTL_NAKSTS_SHIFT) + + +#define DWC_OTG_DIEPCTL_DPID_SHIFT (16) +#define DWC_OTG_DIEPCTL_DPID (1ul << DWC_OTG_DIEPCTL_DPID_SHIFT) + + +#define DWC_OTG_DIEPCTL_EONUM_SHIFT (16) +#define DWC_OTG_DIEPCTL_EONUM (1ul << DWC_OTG_DIEPCTL_EONUM_SHIFT) + + +#define DWC_OTG_DIEPCTL_USBAEP_SHIFT (15) +#define DWC_OTG_DIEPCTL_USBAEP (1 << DWC_OTG_DIEPCTL_USBAEP_SHIFT) + + +#define DWC_OTG_DIEPCTL_MPSIZ_SHIFT (0) +#define DWC_OTG_DIEPCTL_MPSIZ_MASK (0x7ff << (DWC_OTG_DIEPCTL_MPSIZ_SHIFT)) +#define DWC_OTG_DIEPCTL_MPSIZ(v) (((v) << (DWC_OTG_DIEPCTL_MPSIZ_SHIFT)) & (DWC_OTG_DIEPCTL_MPSIZ_MASK)) +#define DWC_OTG_DIEPCTL_MPSIZ_GET(v) (((v) & (DWC_OTG_DIEPCTL_MPSIZ_MASK)) >> (DWC_OTG_DIEPCTL_MPSIZ_SHIFT)) + + +// OTG Device IN Endpoint Interrupt Register +#define DWC_OTG_DIEPxINT(base, x) MMIO32((base) + (0x908) + (0x20*(x))) + +#define DWC_OTG_DIEPINT_TXFE_SHIFT (7) +#define DWC_OTG_DIEPINT_TXFE (1 << DWC_OTG_DIEPINT_TXFE_SHIFT) + + +#define DWC_OTG_DIEPINT_INEPNE_SHIFT (6) +#define DWC_OTG_DIEPINT_INEPNE (1 << DWC_OTG_DIEPINT_INEPNE_SHIFT) + + +#define DWC_OTG_DIEPINT_ITTXFE_SHIFT (4) +#define DWC_OTG_DIEPINT_ITTXFE (1 << DWC_OTG_DIEPINT_ITTXFE_SHIFT) + + +#define DWC_OTG_DIEPINT_TOC_SHIFT (3) +#define DWC_OTG_DIEPINT_TOC (1 << DWC_OTG_DIEPINT_TOC_SHIFT) + + +#define DWC_OTG_DIEPINT_EPDISD_SHIFT (1) +#define DWC_OTG_DIEPINT_EPDISD (1 << DWC_OTG_DIEPINT_EPDISD_SHIFT) + + +#define DWC_OTG_DIEPINT_XFRC_SHIFT (0) +#define DWC_OTG_DIEPINT_XFRC (1 << DWC_OTG_DIEPINT_XFRC_SHIFT) + + +// OTG Device IN Endpoint x Transfer Size Register +#define DWC_OTG_DIEPxTSIZ(base, x) MMIO32((base) + (0x910) + (0x20*(x))) + +#define DWC_OTG_DIEPTSIZ_MC_SHIFT (29) +#define DWC_OTG_DIEPTSIZ_MC_MASK (0x3ul << (DWC_OTG_DIEPTSIZ_MC_SHIFT)) +#define DWC_OTG_DIEPTSIZ_MC(v) (((v) << (DWC_OTG_DIEPTSIZ_MC_SHIFT)) & (DWC_OTG_DIEPTSIZ_MC_MASK)) +#define DWC_OTG_DIEPTSIZ_MC_GET(v) (((v) & (DWC_OTG_DIEPTSIZ_MC_MASK)) >> (DWC_OTG_DIEPTSIZ_MC_SHIFT)) +#define DWC_OTG_DIEPTSIZ_MC_1 DWC_OTG_DIEPTSIZ_MC(0x1) +#define DWC_OTG_DIEPTSIZ_MC_2 DWC_OTG_DIEPTSIZ_MC(0x2) +#define DWC_OTG_DIEPTSIZ_MC_3 DWC_OTG_DIEPTSIZ_MC(0x3) + + +#define DWC_OTG_DIEPTSIZ_PKTCNT_SHIFT (19) +#define DWC_OTG_DIEPTSIZ_PKTCNT_MASK (0x3fful << (DWC_OTG_DIEPTSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DIEPTSIZ_PKTCNT(v) (((v) << (DWC_OTG_DIEPTSIZ_PKTCNT_SHIFT)) & (DWC_OTG_DIEPTSIZ_PKTCNT_MASK)) +#define DWC_OTG_DIEPTSIZ_PKTCNT_GET(v) (((v) & (DWC_OTG_DIEPTSIZ_PKTCNT_MASK)) >> (DWC_OTG_DIEPTSIZ_PKTCNT_SHIFT)) + + +#define DWC_OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) +#define DWC_OTG_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << (DWC_OTG_DIEPTSIZ_XFRSIZ_SHIFT)) +#define DWC_OTG_DIEPTSIZ_XFRSIZ(v) (((v) << (DWC_OTG_DIEPTSIZ_XFRSIZ_SHIFT)) & (DWC_OTG_DIEPTSIZ_XFRSIZ_MASK)) +#define DWC_OTG_DIEPTSIZ_XFRSIZ_GET(v) (((v) & (DWC_OTG_DIEPTSIZ_XFRSIZ_MASK)) >> (DWC_OTG_DIEPTSIZ_XFRSIZ_SHIFT)) + + +#define DWC_OTG_DIEPxDMA(base, x) MMIO32((base) + (0x914) + (0x20*(x))) + +#define DWC_OTG_DIEPxTXFSTS(base, x) MMIO32((base) + (0x918) + (0x20*(x))) + +#define DWC_OTG_DIEPTXFSTS_INEPTFSAV_SHIFT (0) +#define DWC_OTG_DIEPTXFSTS_INEPTFSAV_MASK (0xffff << (DWC_OTG_DIEPTXFSTS_INEPTFSAV_SHIFT)) +#define DWC_OTG_DIEPTXFSTS_INEPTFSAV(v) (((v) << (DWC_OTG_DIEPTXFSTS_INEPTFSAV_SHIFT)) & (DWC_OTG_DIEPTXFSTS_INEPTFSAV_MASK)) +#define DWC_OTG_DIEPTXFSTS_INEPTFSAV_GET(v) (((v) & (DWC_OTG_DIEPTXFSTS_INEPTFSAV_MASK)) >> (DWC_OTG_DIEPTXFSTS_INEPTFSAV_SHIFT)) + + +// OTG Device Control OUT Endpoint x Control Register +#define DWC_OTG_DOEPxCTL(base, x) MMIO32((base) + (0xB00) + (0x20*(x))) + +#define DWC_OTG_DOEPCTL_EPENA_SHIFT (31) +#define DWC_OTG_DOEPCTL_EPENA (1ul << DWC_OTG_DOEPCTL_EPENA_SHIFT) + + +#define DWC_OTG_DOEPCTL_EPDIS_SHIFT (30) +#define DWC_OTG_DOEPCTL_EPDIS (1ul << DWC_OTG_DOEPCTL_EPDIS_SHIFT) + + +#define DWC_OTG_DOEPCTL_SD1PID_SHIFT (29) +#define DWC_OTG_DOEPCTL_SD1PID (1ul << DWC_OTG_DOEPCTL_SD1PID_SHIFT) + + +#define DWC_OTG_DOEPCTL_SODDFRM_SHIFT (29) +#define DWC_OTG_DOEPCTL_SODDFRM (1ul << DWC_OTG_DOEPCTL_SODDFRM_SHIFT) + + +#define DWC_OTG_DOEPCTL_SD0PID_SHIFT (28) +#define DWC_OTG_DOEPCTL_SD0PID (1ul << DWC_OTG_DOEPCTL_SD0PID_SHIFT) + + +#define DWC_OTG_DOEPCTL_SEVNFRM_SHIFT (28) +#define DWC_OTG_DOEPCTL_SEVNFRM (1ul << DWC_OTG_DOEPCTL_SEVNFRM_SHIFT) + + +#define DWC_OTG_DOEPCTL_SNAK_SHIFT (27) +#define DWC_OTG_DOEPCTL_SNAK (1ul << DWC_OTG_DOEPCTL_SNAK_SHIFT) + + +#define DWC_OTG_DOEPCTL_CNAK_SHIFT (26) +#define DWC_OTG_DOEPCTL_CNAK (1ul << DWC_OTG_DOEPCTL_CNAK_SHIFT) + + +#define DWC_OTG_DOEPCTL_STALL_SHIFT (21) +#define DWC_OTG_DOEPCTL_STALL (1ul << DWC_OTG_DOEPCTL_STALL_SHIFT) + + +#define DWC_OTG_DOEPCTL_SNPM_SHIFT (20) +#define DWC_OTG_DOEPCTL_SNPM (1ul << DWC_OTG_DOEPCTL_SNPM_SHIFT) + + +#define DWC_OTG_DOEPCTL_EPTYP_SHIFT (18) +#define DWC_OTG_DOEPCTL_EPTYP_MASK (0x3ul << (DWC_OTG_DOEPCTL_EPTYP_SHIFT)) +#define DWC_OTG_DOEPCTL_EPTYP(v) (((v) << (DWC_OTG_DOEPCTL_EPTYP_SHIFT)) & (DWC_OTG_DOEPCTL_EPTYP_MASK)) +#define DWC_OTG_DOEPCTL_EPTYP_GET(v) (((v) & (DWC_OTG_DOEPCTL_EPTYP_MASK)) >> (DWC_OTG_DOEPCTL_EPTYP_SHIFT)) +#define DWC_OTG_DOEPCTL_EPTYP_CONTROL DWC_OTG_DOEPCTL_EPTYP(0x0) +#define DWC_OTG_DOEPCTL_EPTYP_ISOCHRONOUS DWC_OTG_DOEPCTL_EPTYP(0x1) +#define DWC_OTG_DOEPCTL_EPTYP_BULK DWC_OTG_DOEPCTL_EPTYP(0x2) +#define DWC_OTG_DOEPCTL_EPTYP_INTERRUPT DWC_OTG_DOEPCTL_EPTYP(0x3) + + +#define DWC_OTG_DOEPCTL_NAKSTS_SHIFT (17) +#define DWC_OTG_DOEPCTL_NAKSTS (1ul << DWC_OTG_DOEPCTL_NAKSTS_SHIFT) + + +#define DWC_OTG_DOEPCTL_DPID_SHIFT (16) +#define DWC_OTG_DOEPCTL_DPID (1ul << DWC_OTG_DOEPCTL_DPID_SHIFT) + + +#define DWC_OTG_DOEPCTL_EONUM_SHIFT (16) +#define DWC_OTG_DOEPCTL_EONUM (1ul << DWC_OTG_DOEPCTL_EONUM_SHIFT) + + +#define DWC_OTG_DOEPCTL_USBAEP_SHIFT (15) +#define DWC_OTG_DOEPCTL_USBAEP (1 << DWC_OTG_DOEPCTL_USBAEP_SHIFT) + + +#define DWC_OTG_DOEPCTL_MPSIZ_SHIFT (0) +#define DWC_OTG_DOEPCTL_MPSIZ_MASK (0x7ff << (DWC_OTG_DOEPCTL_MPSIZ_SHIFT)) +#define DWC_OTG_DOEPCTL_MPSIZ(v) (((v) << (DWC_OTG_DOEPCTL_MPSIZ_SHIFT)) & (DWC_OTG_DOEPCTL_MPSIZ_MASK)) +#define DWC_OTG_DOEPCTL_MPSIZ_GET(v) (((v) & (DWC_OTG_DOEPCTL_MPSIZ_MASK)) >> (DWC_OTG_DOEPCTL_MPSIZ_SHIFT)) + + +// OTG Device IN Endpoint Interrupt Register +#define DWC_OTG_DOEPxINT(base, x) MMIO32((base) + (0xB08) + (0x20*(x))) + +#define DWC_OTG_DOEPINT_BBLERR_SHIFT (12) +#define DWC_OTG_DOEPINT_BBLERR (1 << DWC_OTG_DOEPINT_BBLERR_SHIFT) + + +#define DWC_OTG_DOEPINT_B2BSTUP_SHIFT (6) +#define DWC_OTG_DOEPINT_B2BSTUP (1 << DWC_OTG_DOEPINT_B2BSTUP_SHIFT) + + +#define DWC_OTG_DOEPINT_OTEPDIS_SHIFT (4) +#define DWC_OTG_DOEPINT_OTEPDIS (1 << DWC_OTG_DOEPINT_OTEPDIS_SHIFT) + + +#define DWC_OTG_DOEPINT_STUP_SHIFT (3) +#define DWC_OTG_DOEPINT_STUP (1 << DWC_OTG_DOEPINT_STUP_SHIFT) + + +#define DWC_OTG_DOEPINT_EPDISD_SHIFT (1) +#define DWC_OTG_DOEPINT_EPDISD (1 << DWC_OTG_DOEPINT_EPDISD_SHIFT) + + +#define DWC_OTG_DOEPINT_XFRC_SHIFT (0) +#define DWC_OTG_DOEPINT_XFRC (1 << DWC_OTG_DOEPINT_XFRC_SHIFT) + + +// OTG Device OUT Endpoint x Transfer Size Register +#define DWC_OTG_DOEPxTSIZ(base, x) MMIO32((base) + (0xB10) + (0x20*(x))) + +#define DWC_OTG_DOEPTSIZ_STUPCNT_SHIFT (29) +#define DWC_OTG_DOEPTSIZ_STUPCNT_MASK (0x3ul << (DWC_OTG_DOEPTSIZ_STUPCNT_SHIFT)) +#define DWC_OTG_DOEPTSIZ_STUPCNT(v) (((v) << (DWC_OTG_DOEPTSIZ_STUPCNT_SHIFT)) & (DWC_OTG_DOEPTSIZ_STUPCNT_MASK)) +#define DWC_OTG_DOEPTSIZ_STUPCNT_GET(v) (((v) & (DWC_OTG_DOEPTSIZ_STUPCNT_MASK)) >> (DWC_OTG_DOEPTSIZ_STUPCNT_SHIFT)) +#define DWC_OTG_DOEPTSIZ_STUPCNT_1 DWC_OTG_DOEPTSIZ_STUPCNT(0x1) +#define DWC_OTG_DOEPTSIZ_STUPCNT_2 DWC_OTG_DOEPTSIZ_STUPCNT(0x2) +#define DWC_OTG_DOEPTSIZ_STUPCNT_3 DWC_OTG_DOEPTSIZ_STUPCNT(0x3) + + +#define DWC_OTG_DOEPTSIZ_PKTCNT_SHIFT (19) +#define DWC_OTG_DOEPTSIZ_PKTCNT_MASK (0x3fful << (DWC_OTG_DOEPTSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DOEPTSIZ_PKTCNT(v) (((v) << (DWC_OTG_DOEPTSIZ_PKTCNT_SHIFT)) & (DWC_OTG_DOEPTSIZ_PKTCNT_MASK)) +#define DWC_OTG_DOEPTSIZ_PKTCNT_GET(v) (((v) & (DWC_OTG_DOEPTSIZ_PKTCNT_MASK)) >> (DWC_OTG_DOEPTSIZ_PKTCNT_SHIFT)) + + +#define DWC_OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) +#define DWC_OTG_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << (DWC_OTG_DOEPTSIZ_XFRSIZ_SHIFT)) +#define DWC_OTG_DOEPTSIZ_XFRSIZ(v) (((v) << (DWC_OTG_DOEPTSIZ_XFRSIZ_SHIFT)) & (DWC_OTG_DOEPTSIZ_XFRSIZ_MASK)) +#define DWC_OTG_DOEPTSIZ_XFRSIZ_GET(v) (((v) & (DWC_OTG_DOEPTSIZ_XFRSIZ_MASK)) >> (DWC_OTG_DOEPTSIZ_XFRSIZ_SHIFT)) + + +#define DWC_OTG_DOEPxDMA(base, x) MMIO32((base) + (0xB14) + (0x20*(x))) + +#define DWC_OTG_DIEP0CTL(base) MMIO32((base) + (0x900)) + +#define DWC_OTG_DIEP0CTL_EPENA_SHIFT (31) +#define DWC_OTG_DIEP0CTL_EPENA (1ul << DWC_OTG_DIEP0CTL_EPENA_SHIFT) + + +#define DWC_OTG_DIEP0CTL_EPDIS_SHIFT (30) +#define DWC_OTG_DIEP0CTL_EPDIS (1ul << DWC_OTG_DIEP0CTL_EPDIS_SHIFT) + + +#define DWC_OTG_DIEP0CTL_SNAK_SHIFT (27) +#define DWC_OTG_DIEP0CTL_SNAK (1ul << DWC_OTG_DIEP0CTL_SNAK_SHIFT) + + +#define DWC_OTG_DIEP0CTL_CNAK_SHIFT (26) +#define DWC_OTG_DIEP0CTL_CNAK (1ul << DWC_OTG_DIEP0CTL_CNAK_SHIFT) + + +#define DWC_OTG_DIEP0CTL_TXFNUM_SHIFT (22) +#define DWC_OTG_DIEP0CTL_TXFNUM_MASK (0xful << (DWC_OTG_DIEP0CTL_TXFNUM_SHIFT)) +#define DWC_OTG_DIEP0CTL_TXFNUM(v) (((v) << (DWC_OTG_DIEP0CTL_TXFNUM_SHIFT)) & (DWC_OTG_DIEP0CTL_TXFNUM_MASK)) +#define DWC_OTG_DIEP0CTL_TXFNUM_GET(v) (((v) & (DWC_OTG_DIEP0CTL_TXFNUM_MASK)) >> (DWC_OTG_DIEP0CTL_TXFNUM_SHIFT)) + + +#define DWC_OTG_DIEP0CTL_STALL_SHIFT (21) +#define DWC_OTG_DIEP0CTL_STALL (1ul << DWC_OTG_DIEP0CTL_STALL_SHIFT) + + +#define DWC_OTG_DIEP0CTL_EPTYP_SHIFT (18) +#define DWC_OTG_DIEP0CTL_EPTYP_MASK (0x3ul << (DWC_OTG_DIEP0CTL_EPTYP_SHIFT)) +#define DWC_OTG_DIEP0CTL_EPTYP(v) (((v) << (DWC_OTG_DIEP0CTL_EPTYP_SHIFT)) & (DWC_OTG_DIEP0CTL_EPTYP_MASK)) +#define DWC_OTG_DIEP0CTL_EPTYP_GET(v) (((v) & (DWC_OTG_DIEP0CTL_EPTYP_MASK)) >> (DWC_OTG_DIEP0CTL_EPTYP_SHIFT)) +#define DWC_OTG_DIEP0CTL_EPTYP_CONTROL DWC_OTG_DIEP0CTL_EPTYP(0x0) + + +#define DWC_OTG_DIEP0CTL_NAKSTS_SHIFT (17) +#define DWC_OTG_DIEP0CTL_NAKSTS (1ul << DWC_OTG_DIEP0CTL_NAKSTS_SHIFT) + + +#define DWC_OTG_DIEP0CTL_USBAEP_SHIFT (15) +#define DWC_OTG_DIEP0CTL_USBAEP (1 << DWC_OTG_DIEP0CTL_USBAEP_SHIFT) + + +#define DWC_OTG_DIEP0CTL_MPSIZ_SHIFT (0) +#define DWC_OTG_DIEP0CTL_MPSIZ_MASK (0x3 << (DWC_OTG_DIEP0CTL_MPSIZ_SHIFT)) +#define DWC_OTG_DIEP0CTL_MPSIZ(v) (((v) << (DWC_OTG_DIEP0CTL_MPSIZ_SHIFT)) & (DWC_OTG_DIEP0CTL_MPSIZ_MASK)) +#define DWC_OTG_DIEP0CTL_MPSIZ_GET(v) (((v) & (DWC_OTG_DIEP0CTL_MPSIZ_MASK)) >> (DWC_OTG_DIEP0CTL_MPSIZ_SHIFT)) +#define DWC_OTG_DIEP0CTL_MPSIZ_64 DWC_OTG_DIEP0CTL_MPSIZ(0x0) +#define DWC_OTG_DIEP0CTL_MPSIZ_32 DWC_OTG_DIEP0CTL_MPSIZ(0x1) +#define DWC_OTG_DIEP0CTL_MPSIZ_16 DWC_OTG_DIEP0CTL_MPSIZ(0x2) +#define DWC_OTG_DIEP0CTL_MPSIZ_8 DWC_OTG_DIEP0CTL_MPSIZ(0x3) + + +#define DWC_OTG_DIEP0TSIZ(base) MMIO32((base) + (0x910)) + +#define DWC_OTG_DIEP0TSIZ_PKTCNT_SHIFT (19) +#define DWC_OTG_DIEP0TSIZ_PKTCNT_MASK (0x3ul << (DWC_OTG_DIEP0TSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DIEP0TSIZ_PKTCNT(v) (((v) << (DWC_OTG_DIEP0TSIZ_PKTCNT_SHIFT)) & (DWC_OTG_DIEP0TSIZ_PKTCNT_MASK)) +#define DWC_OTG_DIEP0TSIZ_PKTCNT_GET(v) (((v) & (DWC_OTG_DIEP0TSIZ_PKTCNT_MASK)) >> (DWC_OTG_DIEP0TSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DIEP0TSIZ_PKTCNT_1 DWC_OTG_DIEP0TSIZ_PKTCNT(0x1) + + +#define DWC_OTG_DIEP0TSIZ_XFRSIZ_SHIFT (0) +#define DWC_OTG_DIEP0TSIZ_XFRSIZ_MASK (0x7f << (DWC_OTG_DIEP0TSIZ_XFRSIZ_SHIFT)) +#define DWC_OTG_DIEP0TSIZ_XFRSIZ(v) (((v) << (DWC_OTG_DIEP0TSIZ_XFRSIZ_SHIFT)) & (DWC_OTG_DIEP0TSIZ_XFRSIZ_MASK)) +#define DWC_OTG_DIEP0TSIZ_XFRSIZ_GET(v) (((v) & (DWC_OTG_DIEP0TSIZ_XFRSIZ_MASK)) >> (DWC_OTG_DIEP0TSIZ_XFRSIZ_SHIFT)) + + +// OTG Device Control OUT Endpoint 0 Control Register +#define DWC_OTG_DOEP0CTL(base) MMIO32((base) + (0xB00)) + +#define DWC_OTG_DOEP0CTL_EPENA_SHIFT (31) +#define DWC_OTG_DOEP0CTL_EPENA (1ul << DWC_OTG_DOEP0CTL_EPENA_SHIFT) + + +#define DWC_OTG_DOEP0CTL_EPDIS_SHIFT (30) +#define DWC_OTG_DOEP0CTL_EPDIS (1ul << DWC_OTG_DOEP0CTL_EPDIS_SHIFT) + + +#define DWC_OTG_DOEP0CTL_SNAK_SHIFT (27) +#define DWC_OTG_DOEP0CTL_SNAK (1ul << DWC_OTG_DOEP0CTL_SNAK_SHIFT) + + +#define DWC_OTG_DOEP0CTL_CNAK_SHIFT (26) +#define DWC_OTG_DOEP0CTL_CNAK (1ul << DWC_OTG_DOEP0CTL_CNAK_SHIFT) + + +#define DWC_OTG_DOEP0CTL_STALL_SHIFT (21) +#define DWC_OTG_DOEP0CTL_STALL (1ul << DWC_OTG_DOEP0CTL_STALL_SHIFT) + + +#define DWC_OTG_DOEP0CTL_SNPM_SHIFT (20) +#define DWC_OTG_DOEP0CTL_SNPM (1ul << DWC_OTG_DOEP0CTL_SNPM_SHIFT) + + +#define DWC_OTG_DOEP0CTL_EPTYP_SHIFT (18) +#define DWC_OTG_DOEP0CTL_EPTYP_MASK (0x3ul << (DWC_OTG_DOEP0CTL_EPTYP_SHIFT)) +#define DWC_OTG_DOEP0CTL_EPTYP(v) (((v) << (DWC_OTG_DOEP0CTL_EPTYP_SHIFT)) & (DWC_OTG_DOEP0CTL_EPTYP_MASK)) +#define DWC_OTG_DOEP0CTL_EPTYP_GET(v) (((v) & (DWC_OTG_DOEP0CTL_EPTYP_MASK)) >> (DWC_OTG_DOEP0CTL_EPTYP_SHIFT)) +#define DWC_OTG_DOEP0CTL_EPTYP_CONTROL DWC_OTG_DOEP0CTL_EPTYP(0x0) + + +#define DWC_OTG_DOEP0CTL_NAKSTS_SHIFT (17) +#define DWC_OTG_DOEP0CTL_NAKSTS (1ul << DWC_OTG_DOEP0CTL_NAKSTS_SHIFT) + + +#define DWC_OTG_DOEP0CTL_USBAEP_SHIFT (15) +#define DWC_OTG_DOEP0CTL_USBAEP (1 << DWC_OTG_DOEP0CTL_USBAEP_SHIFT) + + +#define DWC_OTG_DOEP0CTL_MPSIZ_SHIFT (0) +#define DWC_OTG_DOEP0CTL_MPSIZ_MASK (0x3 << (DWC_OTG_DOEP0CTL_MPSIZ_SHIFT)) +#define DWC_OTG_DOEP0CTL_MPSIZ(v) (((v) << (DWC_OTG_DOEP0CTL_MPSIZ_SHIFT)) & (DWC_OTG_DOEP0CTL_MPSIZ_MASK)) +#define DWC_OTG_DOEP0CTL_MPSIZ_GET(v) (((v) & (DWC_OTG_DOEP0CTL_MPSIZ_MASK)) >> (DWC_OTG_DOEP0CTL_MPSIZ_SHIFT)) +#define DWC_OTG_DOEP0CTL_MPSIZ_64 DWC_OTG_DOEP0CTL_MPSIZ(0x0) +#define DWC_OTG_DOEP0CTL_MPSIZ_32 DWC_OTG_DOEP0CTL_MPSIZ(0x1) +#define DWC_OTG_DOEP0CTL_MPSIZ_16 DWC_OTG_DOEP0CTL_MPSIZ(0x2) +#define DWC_OTG_DOEP0CTL_MPSIZ_8 DWC_OTG_DOEP0CTL_MPSIZ(0x3) + + +#define DWC_OTG_DOEP0TSIZ(base) MMIO32((base) + (0xB10)) + +#define DWC_OTG_DOEP0TSIZ_STUPCNT_SHIFT (29) +#define DWC_OTG_DOEP0TSIZ_STUPCNT_MASK (0x3ul << (DWC_OTG_DOEP0TSIZ_STUPCNT_SHIFT)) +#define DWC_OTG_DOEP0TSIZ_STUPCNT(v) (((v) << (DWC_OTG_DOEP0TSIZ_STUPCNT_SHIFT)) & (DWC_OTG_DOEP0TSIZ_STUPCNT_MASK)) +#define DWC_OTG_DOEP0TSIZ_STUPCNT_GET(v) (((v) & (DWC_OTG_DOEP0TSIZ_STUPCNT_MASK)) >> (DWC_OTG_DOEP0TSIZ_STUPCNT_SHIFT)) +#define DWC_OTG_DOEP0TSIZ_STUPCNT_1 DWC_OTG_DOEP0TSIZ_STUPCNT(0x1) +#define DWC_OTG_DOEP0TSIZ_STUPCNT_2 DWC_OTG_DOEP0TSIZ_STUPCNT(0x2) +#define DWC_OTG_DOEP0TSIZ_STUPCNT_3 DWC_OTG_DOEP0TSIZ_STUPCNT(0x3) + + +#define DWC_OTG_DOEP0TSIZ_PKTCNT_SHIFT (19) +#define DWC_OTG_DOEP0TSIZ_PKTCNT_MASK (0x3ul << (DWC_OTG_DOEP0TSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DOEP0TSIZ_PKTCNT(v) (((v) << (DWC_OTG_DOEP0TSIZ_PKTCNT_SHIFT)) & (DWC_OTG_DOEP0TSIZ_PKTCNT_MASK)) +#define DWC_OTG_DOEP0TSIZ_PKTCNT_GET(v) (((v) & (DWC_OTG_DOEP0TSIZ_PKTCNT_MASK)) >> (DWC_OTG_DOEP0TSIZ_PKTCNT_SHIFT)) +#define DWC_OTG_DOEP0TSIZ_PKTCNT_1 DWC_OTG_DOEP0TSIZ_PKTCNT(0x1) + + +#define DWC_OTG_DOEP0TSIZ_XFRSIZ_SHIFT (0) +#define DWC_OTG_DOEP0TSIZ_XFRSIZ_MASK (0x7f << (DWC_OTG_DOEP0TSIZ_XFRSIZ_SHIFT)) +#define DWC_OTG_DOEP0TSIZ_XFRSIZ(v) (((v) << (DWC_OTG_DOEP0TSIZ_XFRSIZ_SHIFT)) & (DWC_OTG_DOEP0TSIZ_XFRSIZ_MASK)) +#define DWC_OTG_DOEP0TSIZ_XFRSIZ_GET(v) (((v) & (DWC_OTG_DOEP0TSIZ_XFRSIZ_MASK)) >> (DWC_OTG_DOEP0TSIZ_XFRSIZ_SHIFT)) + + +// Power and clock gating control and status register +#define DWC_OTG_PCGCCTL(base) MMIO32((base) + (0xE00)) + +// Stop PHY clock. The application sets this bit to stop the PHY clock when the USB is suspended, the session +// is not valid, or the device is disconnected. +// The application clears this bit when the USB is resumed or a new session starts //STM32F4 +#define DWC_OTG_PCGCCTL_STPPCLK_SHIFT (0) +#define DWC_OTG_PCGCCTL_STPPCLK (1 << DWC_OTG_PCGCCTL_STPPCLK_SHIFT) + + +// Gate HCLK. The application sets this bit to gate HCLK to modules other than the AHB Slave and Master +// and wakeup logic when the USB is suspended or the session is not valid. +// The application clears this bit when the USB is resumed or a new session starts. //STM32F4 +#define DWC_OTG_PCGCCTL_GATEHCLK_SHIFT (1) +#define DWC_OTG_PCGCCTL_GATEHCLK (1 << DWC_OTG_PCGCCTL_GATEHCLK_SHIFT) + + +// Indicates that the PHY has been suspended. +#define DWC_OTG_PCGCCTL_PHYSUSP_SHIFT (4) +#define DWC_OTG_PCGCCTL_PHYSUSP (1 << DWC_OTG_PCGCCTL_PHYSUSP_SHIFT) + + +// Data FIFO +#define DWC_OTG_FIFO(base, x) MMIO32((base) + (0x1000) + ((x) << 12)) + + +#endif diff --git a/include/unicore-mx/common/dwc_otg.ucd b/include/unicore-mx/common/dwc_otg.ucd index 2ce16e35..c367fbd7 100644 --- a/include/unicore-mx/common/dwc_otg.ucd +++ b/include/unicore-mx/common/dwc_otg.ucd @@ -99,7 +99,7 @@ bit AHBIDL 31 bits name TXFNUM size 5 - offset 16 + offset 6 value ALL 0x10 bit TXFFLSH 5 @@ -495,7 +495,8 @@ reg DCTL 0x804 bit POPRGDNE 11 bit CGONAK 10 bit SGONAK 9 -bit SGINAK 8 +bit CGINAK 8 +bit SGINAK 7 bits TCTL 3 4 bit GONSTS 3 bit GINSTS 2 diff --git a/lib/usbd/backend/usbd_dwc_otg.c b/lib/usbd/backend/usbd_dwc_otg.c index ebb42f89..313c1891 100644 --- a/lib/usbd/backend/usbd_dwc_otg.c +++ b/lib/usbd/backend/usbd_dwc_otg.c @@ -109,12 +109,25 @@ static inline uint16_t get_fifo_depth(usbd_device *dev) */ static void flush_fifo(usbd_device *dev) { + // Set Global IN OUT ep NACK + REBASE(DWC_OTG_DCTL) = DWC_OTG_DCTL_SGONAK | DWC_OTG_DCTL_SGINAK; + + /* Wait for AHB idle. */ + while (!(REBASE(DWC_OTG_GRSTCTL) & DWC_OTG_GRSTCTL_AHBIDL)); + + const uint32_t GNACKEFF = DWC_OTG_GINTMSK_GINAKEFFM ; // | DWC_OTG_GINTMSK_GONAKEFFM ; + // Wait Global NACK Effective + while ( (REBASE(DWC_OTG_GINTSTS) & GNACKEFF) != GNACKEFF ); + /* Flush RX, TX FIFO */ REBASE(DWC_OTG_GRSTCTL) = DWC_OTG_GRSTCTL_RXFFLSH | (DWC_OTG_GRSTCTL_TXFFLSH | DWC_OTG_GRSTCTL_TXFNUM_ALL); - while (REBASE(DWC_OTG_GRSTCTL) & - (DWC_OTG_GRSTCTL_RXFFLSH | DWC_OTG_GRSTCTL_TXFFLSH)); + const uint32_t XFLUSH = (DWC_OTG_GRSTCTL_RXFFLSH | DWC_OTG_GRSTCTL_TXFFLSH); + while ( (REBASE(DWC_OTG_GRSTCTL) & XFLUSH) != 0 ); + + // Clear Global IN OUT ep NACK + REBASE(DWC_OTG_DCTL) = DWC_OTG_DCTL_CGONAK | DWC_OTG_DCTL_CGINAK; } void dwc_otg_init(usbd_device *dev) From 95297d8456ca0308fd1d51cf0ebd36220c6a4714 Mon Sep 17 00:00:00 2001 From: alexrayne Date: Tue, 14 Mar 2017 21:47:55 +0200 Subject: [PATCH 2/2] !usbd:dwc_otg:fifo_flush - skip unpredictable behaviour of GxNACKEFF status, waiting for them can hang --- lib/usbd/backend/usbd_dwc_otg.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/lib/usbd/backend/usbd_dwc_otg.c b/lib/usbd/backend/usbd_dwc_otg.c index 313c1891..655fc862 100644 --- a/lib/usbd/backend/usbd_dwc_otg.c +++ b/lib/usbd/backend/usbd_dwc_otg.c @@ -109,15 +109,25 @@ static inline uint16_t get_fifo_depth(usbd_device *dev) */ static void flush_fifo(usbd_device *dev) { + USBD_LOG_LN(USB_VSETUP,"USBD:Flush"); + + const uint32_t GINACKEFF = DWC_OTG_GINTMSK_GINAKEFFM ; // | DWC_OTG_GINTMSK_GONAKEFFM ; + const uint32_t GNACKEFF = DWC_OTG_GINTMSK_GINAKEFFM | DWC_OTG_GINTMSK_GONAKEFFM ; + if ( (REBASE(DWC_OTG_GINTSTS) & GNACKEFF) != 0 ){ + // Clear Global IN OUT ep NACK if it alredy set + REBASE(DWC_OTG_DCTL) = DWC_OTG_DCTL_CGONAK | DWC_OTG_DCTL_CGINAK; + while ( (REBASE(DWC_OTG_GINTSTS) & GNACKEFF) != 0 ) ; + } + // Set Global IN OUT ep NACK REBASE(DWC_OTG_DCTL) = DWC_OTG_DCTL_SGONAK | DWC_OTG_DCTL_SGINAK; /* Wait for AHB idle. */ while (!(REBASE(DWC_OTG_GRSTCTL) & DWC_OTG_GRSTCTL_AHBIDL)); - const uint32_t GNACKEFF = DWC_OTG_GINTMSK_GINAKEFFM ; // | DWC_OTG_GINTMSK_GONAKEFFM ; - // Wait Global NACK Effective - while ( (REBASE(DWC_OTG_GINTSTS) & GNACKEFF) != GNACKEFF ); + // Wait Global NACK Effective. it is demanded by RM0090 but unpredictable and can hang! + if (0) + while ( (REBASE(DWC_OTG_GINTSTS) & GINACKEFF) != GINACKEFF ); /* Flush RX, TX FIFO */ REBASE(DWC_OTG_GRSTCTL) = DWC_OTG_GRSTCTL_RXFFLSH |