Skip to content

Commit 0bdd799

Browse files
matttbematttbe
committed
tgupdate: merge t/DO-NOT-MERGE-mptcp-use-kmalloc-on-kasan-build base into t/DO-NOT-MERGE-mptcp-use-kmalloc-on-kasan-build
2 parents 7939a8d + 440923d commit 0bdd799

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

51 files changed

+4409
-3981
lines changed

‎drivers/net/ethernet/realtek/r8169_main.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@
5757
#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
5858
#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
5959
#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
60+
#define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw"
6061
#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
6162
#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
6263
#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
@@ -110,6 +111,7 @@ static const struct rtl_chip_info {
110111
{ 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
111112

112113
/* 8125D family. */
114+
{ 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 },
113115
{ 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 },
114116
{ 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 },
115117

@@ -770,6 +772,7 @@ MODULE_FIRMWARE(FIRMWARE_8125A_3);
770772
MODULE_FIRMWARE(FIRMWARE_8125B_2);
771773
MODULE_FIRMWARE(FIRMWARE_8125D_1);
772774
MODULE_FIRMWARE(FIRMWARE_8125D_2);
775+
MODULE_FIRMWARE(FIRMWARE_8125K_1);
773776
MODULE_FIRMWARE(FIRMWARE_8125BP_2);
774777
MODULE_FIRMWARE(FIRMWARE_8126A_2);
775778
MODULE_FIRMWARE(FIRMWARE_8126A_3);

‎drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,6 @@
3838
#define GMAC_SHUT BIT(6)
3939

4040
#define PHY_INTF_SELI GENMASK(30, 28)
41-
#define PHY_INTF_MII FIELD_PREP(PHY_INTF_SELI, 0)
42-
#define PHY_INTF_RMII FIELD_PREP(PHY_INTF_SELI, 4)
4341

4442
struct ls1x_dwmac {
4543
struct plat_stmmacenet_data *plat_dat;
@@ -140,22 +138,18 @@ static int ls1c_dwmac_syscon_init(struct platform_device *pdev, void *priv)
140138
struct ls1x_dwmac *dwmac = priv;
141139
struct plat_stmmacenet_data *plat = dwmac->plat_dat;
142140
struct regmap *regmap = dwmac->regmap;
141+
int phy_intf_sel;
143142

144-
switch (plat->phy_interface) {
145-
case PHY_INTERFACE_MODE_MII:
146-
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
147-
PHY_INTF_MII);
148-
break;
149-
case PHY_INTERFACE_MODE_RMII:
150-
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
151-
PHY_INTF_RMII);
152-
break;
153-
default:
143+
phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_interface);
144+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
145+
phy_intf_sel != PHY_INTF_SEL_RMII) {
154146
dev_err(&pdev->dev, "Unsupported PHY-mode %u\n",
155147
plat->phy_interface);
156148
return -EOPNOTSUPP;
157149
}
158150

151+
regmap_update_bits(regmap, LS1X_SYSCON1, PHY_INTF_SELI,
152+
FIELD_PREP(PHY_INTF_SELI, phy_intf_sel));
159153
regmap_update_bits(regmap, LS1X_SYSCON0, GMAC0_SHUT, 0);
160154

161155
return 0;

‎drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c‎

Lines changed: 28 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,6 @@
1717

1818
/* Peri Configuration register for mt2712 */
1919
#define PERI_ETH_PHY_INTF_SEL 0x418
20-
#define PHY_INTF_MII 0
21-
#define PHY_INTF_RGMII 1
22-
#define PHY_INTF_RMII 4
2320
#define RMII_CLK_SRC_RXC BIT(4)
2421
#define RMII_CLK_SRC_INTERNAL BIT(5)
2522

@@ -88,7 +85,8 @@ struct mediatek_dwmac_plat_data {
8885
};
8986

9087
struct mediatek_dwmac_variant {
91-
int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
88+
int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat,
89+
u8 phy_intf_sel);
9290
int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
9391

9492
/* clock ids to be requested */
@@ -109,29 +107,16 @@ static const char * const mt8195_dwmac_clk_l[] = {
109107
"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
110108
};
111109

112-
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
110+
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
111+
u8 phy_intf_sel)
113112
{
114-
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
115-
int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
116-
u32 intf_val = 0;
113+
u32 intf_val = phy_intf_sel;
117114

118-
/* select phy interface in top control domain */
119-
switch (plat->phy_mode) {
120-
case PHY_INTERFACE_MODE_MII:
121-
intf_val |= PHY_INTF_MII;
122-
break;
123-
case PHY_INTERFACE_MODE_RMII:
124-
intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
125-
break;
126-
case PHY_INTERFACE_MODE_RGMII:
127-
case PHY_INTERFACE_MODE_RGMII_TXID:
128-
case PHY_INTERFACE_MODE_RGMII_RXID:
129-
case PHY_INTERFACE_MODE_RGMII_ID:
130-
intf_val |= PHY_INTF_RGMII;
131-
break;
132-
default:
133-
dev_err(plat->dev, "phy interface not supported\n");
134-
return -EINVAL;
115+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
116+
if (plat->rmii_clk_from_mac)
117+
intf_val |= RMII_CLK_SRC_INTERNAL;
118+
if (plat->rmii_rxc)
119+
intf_val |= RMII_CLK_SRC_RXC;
135120
}
136121

137122
regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
@@ -288,30 +273,16 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
288273
.tx_delay_max = 17600,
289274
};
290275

291-
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
276+
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
277+
u8 phy_intf_sel)
292278
{
293-
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
294-
int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
295-
u32 intf_val = 0;
279+
u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);
296280

297-
/* select phy interface in top control domain */
298-
switch (plat->phy_mode) {
299-
case PHY_INTERFACE_MODE_MII:
300-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
301-
break;
302-
case PHY_INTERFACE_MODE_RMII:
303-
intf_val |= (rmii_rxc | rmii_clk_from_mac);
304-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
305-
break;
306-
case PHY_INTERFACE_MODE_RGMII:
307-
case PHY_INTERFACE_MODE_RGMII_TXID:
308-
case PHY_INTERFACE_MODE_RGMII_RXID:
309-
case PHY_INTERFACE_MODE_RGMII_ID:
310-
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
311-
break;
312-
default:
313-
dev_err(plat->dev, "phy interface not supported\n");
314-
return -EINVAL;
281+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
282+
if (plat->rmii_clk_from_mac)
283+
intf_val |= MT8195_RMII_CLK_SRC_INTERNAL;
284+
if (plat->rmii_rxc)
285+
intf_val |= MT8195_RMII_CLK_SRC_RXC;
315286
}
316287

317288
/* MT8195 only support external PHY */
@@ -527,10 +498,18 @@ static int mediatek_dwmac_init(struct device *dev, void *priv)
527498
{
528499
struct mediatek_dwmac_plat_data *plat = priv;
529500
const struct mediatek_dwmac_variant *variant = plat->variant;
530-
int ret;
501+
int phy_intf_sel, ret;
531502

532503
if (variant->dwmac_set_phy_interface) {
533-
ret = variant->dwmac_set_phy_interface(plat);
504+
phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_mode);
505+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
506+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
507+
phy_intf_sel != PHY_INTF_SEL_RMII) {
508+
dev_err(plat->dev, "phy interface not supported\n");
509+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
510+
}
511+
512+
ret = variant->dwmac_set_phy_interface(plat, phy_intf_sel);
534513
if (ret) {
535514
dev_err(dev, "failed to set phy interface, err = %d\n", ret);
536515
return ret;

‎drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c‎

Lines changed: 6 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,6 @@
1515

1616
#include "stmmac_platform.h"
1717

18-
#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
19-
#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
2018
#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
2119

2220
#define JH7100_SYSMAIN_REGISTER49_DLYCHAIN 0xc8
@@ -35,25 +33,15 @@ static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
3533
struct starfive_dwmac *dwmac = plat_dat->bsp_priv;
3634
struct regmap *regmap;
3735
unsigned int args[2];
38-
unsigned int mode;
36+
int phy_intf_sel;
3937
int err;
4038

41-
switch (plat_dat->phy_interface) {
42-
case PHY_INTERFACE_MODE_RMII:
43-
mode = STARFIVE_DWMAC_PHY_INFT_RMII;
44-
break;
45-
46-
case PHY_INTERFACE_MODE_RGMII:
47-
case PHY_INTERFACE_MODE_RGMII_ID:
48-
case PHY_INTERFACE_MODE_RGMII_RXID:
49-
case PHY_INTERFACE_MODE_RGMII_TXID:
50-
mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
51-
break;
52-
53-
default:
39+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
40+
if (phy_intf_sel != PHY_INTF_SEL_RGMII &&
41+
phy_intf_sel != PHY_INTF_SEL_RMII) {
5442
dev_err(dwmac->dev, "unsupported interface %s\n",
5543
phy_modes(plat_dat->phy_interface));
56-
return -EINVAL;
44+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
5745
}
5846

5947
regmap = syscon_regmap_lookup_by_phandle_args(dwmac->dev->of_node,
@@ -65,7 +53,7 @@ static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
6553
/* args[0]:offset args[1]: shift */
6654
err = regmap_update_bits(regmap, args[0],
6755
STARFIVE_DWMAC_PHY_INFT_FIELD << args[1],
68-
mode << args[1]);
56+
phy_intf_sel << args[1]);
6957
if (err)
7058
return dev_err_probe(dwmac->dev, err, "error setting phy mode\n");
7159

‎drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c‎

Lines changed: 24 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -47,23 +47,18 @@
4747
*------------------------------------------
4848
*/
4949
#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
50-
#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
51-
#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
52-
#define SYSCFG_PMCR_ETH_SEL_GMII 0
50+
#define SYSCFG_PMCR_PHY_INTF_SEL_MASK GENMASK(23, 21)
5351
#define SYSCFG_MCU_ETH_SEL_MII 0
5452
#define SYSCFG_MCU_ETH_SEL_RMII 1
5553

5654
/* STM32MP2 register definitions */
5755
#define SYSCFG_MP2_ETH_MASK GENMASK(31, 0)
5856

57+
#define SYSCFG_ETHCR_ETH_SEL_MASK GENMASK(6, 4)
5958
#define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2)
6059
#define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1)
6160
#define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0)
6261

63-
#define SYSCFG_ETHCR_ETH_SEL_MII 0
64-
#define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4)
65-
#define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6)
66-
6762
/* STM32MPx register definitions
6863
*
6964
* Below table summarizes the clock requirement and clock sources for
@@ -232,11 +227,14 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
232227
return -EINVAL;
233228
}
234229

235-
static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
230+
static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat,
231+
u8 phy_intf_sel)
236232
{
237233
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
238234
u32 reg = dwmac->mode_reg;
239-
int val = 0;
235+
int val;
236+
237+
val = FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, phy_intf_sel);
240238

241239
switch (plat_dat->phy_interface) {
242240
case PHY_INTERFACE_MODE_MII:
@@ -250,20 +248,17 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
250248
val |= SYSCFG_PMCR_ETH_SEL_MII;
251249
break;
252250
case PHY_INTERFACE_MODE_GMII:
253-
val = SYSCFG_PMCR_ETH_SEL_GMII;
254251
if (dwmac->enable_eth_ck)
255252
val |= SYSCFG_PMCR_ETH_CLK_SEL;
256253
break;
257254
case PHY_INTERFACE_MODE_RMII:
258-
val = SYSCFG_PMCR_ETH_SEL_RMII;
259255
if (dwmac->enable_eth_ck)
260256
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
261257
break;
262258
case PHY_INTERFACE_MODE_RGMII:
263259
case PHY_INTERFACE_MODE_RGMII_ID:
264260
case PHY_INTERFACE_MODE_RGMII_RXID:
265261
case PHY_INTERFACE_MODE_RGMII_TXID:
266-
val = SYSCFG_PMCR_ETH_SEL_RGMII;
267262
if (dwmac->enable_eth_ck)
268263
val |= SYSCFG_PMCR_ETH_CLK_SEL;
269264
break;
@@ -288,18 +283,20 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
288283
dwmac->mode_mask, val);
289284
}
290285

291-
static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
286+
static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat,
287+
u8 phy_intf_sel)
292288
{
293289
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
294290
u32 reg = dwmac->mode_reg;
295-
int val = 0;
291+
int val;
292+
293+
val = FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, phy_intf_sel);
296294

297295
switch (plat_dat->phy_interface) {
298296
case PHY_INTERFACE_MODE_MII:
299297
/* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */
300298
break;
301299
case PHY_INTERFACE_MODE_RMII:
302-
val = SYSCFG_ETHCR_ETH_SEL_RMII;
303300
if (dwmac->enable_eth_ck) {
304301
/* Internal clock ETH_CLK of 50MHz from RCC is used */
305302
val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;
@@ -309,8 +306,6 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
309306
case PHY_INTERFACE_MODE_RGMII_ID:
310307
case PHY_INTERFACE_MODE_RGMII_RXID:
311308
case PHY_INTERFACE_MODE_RGMII_TXID:
312-
val = SYSCFG_ETHCR_ETH_SEL_RGMII;
313-
fallthrough;
314309
case PHY_INTERFACE_MODE_GMII:
315310
if (dwmac->enable_eth_ck) {
316311
/* Internal clock ETH_CLK of 125MHz from RCC is used */
@@ -337,7 +332,7 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
337332
static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
338333
{
339334
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
340-
int ret;
335+
int phy_intf_sel, ret;
341336

342337
ret = stm32mp1_select_ethck_external(plat_dat);
343338
if (ret)
@@ -347,10 +342,19 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
347342
if (ret)
348343
return ret;
349344

345+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
346+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
347+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
348+
phy_intf_sel != PHY_INTF_SEL_RMII) {
349+
dev_err(dwmac->dev, "Mode %s not supported\n",
350+
phy_modes(plat_dat->phy_interface));
351+
return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
352+
}
353+
350354
if (!dwmac->ops->is_mp2)
351-
return stm32mp1_configure_pmcr(plat_dat);
355+
return stm32mp1_configure_pmcr(plat_dat, phy_intf_sel);
352356
else
353-
return stm32mp2_configure_syscfg(plat_dat);
357+
return stm32mp2_configure_syscfg(plat_dat, phy_intf_sel);
354358
}
355359

356360
static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)

‎drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c‎

Lines changed: 6 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -42,10 +42,6 @@
4242

4343
#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)
4444

45-
#define ETHER_CONFIG_INTF_MII 0
46-
#define ETHER_CONFIG_INTF_RGMII BIT(0)
47-
#define ETHER_CONFIG_INTF_RMII BIT(2)
48-
4945
struct visconti_eth {
5046
void __iomem *reg;
5147
struct clk *phy_ref_clk;
@@ -150,22 +146,12 @@ static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmac
150146
{
151147
struct visconti_eth *dwmac = plat_dat->bsp_priv;
152148
unsigned int clk_sel_val;
153-
u32 phy_intf_sel;
154-
155-
switch (plat_dat->phy_interface) {
156-
case PHY_INTERFACE_MODE_RGMII:
157-
case PHY_INTERFACE_MODE_RGMII_ID:
158-
case PHY_INTERFACE_MODE_RGMII_RXID:
159-
case PHY_INTERFACE_MODE_RGMII_TXID:
160-
phy_intf_sel = ETHER_CONFIG_INTF_RGMII;
161-
break;
162-
case PHY_INTERFACE_MODE_MII:
163-
phy_intf_sel = ETHER_CONFIG_INTF_MII;
164-
break;
165-
case PHY_INTERFACE_MODE_RMII:
166-
phy_intf_sel = ETHER_CONFIG_INTF_RMII;
167-
break;
168-
default:
149+
int phy_intf_sel;
150+
151+
phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
152+
if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
153+
phy_intf_sel != PHY_INTF_SEL_RGMII &&
154+
phy_intf_sel != PHY_INTF_SEL_RMII) {
169155
dev_err(&pdev->dev, "Unsupported phy-mode (%d)\n", plat_dat->phy_interface);
170156
return -EOPNOTSUPP;
171157
}

0 commit comments

Comments
 (0)