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10 | 10 | #define __KVM_VCPU_RISCV_PMU_H |
11 | 11 |
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12 | 12 | #include <linux/perf/riscv_pmu.h> |
| 13 | +#include <asm/kvm_vcpu_insn.h> |
13 | 14 | #include <asm/sbi.h> |
14 | 15 |
|
15 | 16 | #ifdef CONFIG_RISCV_PMU_SBI |
@@ -64,11 +65,11 @@ struct kvm_pmu { |
64 | 65 |
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65 | 66 | #if defined(CONFIG_32BIT) |
66 | 67 | #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ |
67 | | -{.base = CSR_CYCLEH, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, \ |
68 | | -{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, |
| 68 | +{.base = CSR_CYCLEH, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, \ |
| 69 | +{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, |
69 | 70 | #else |
70 | 71 | #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ |
71 | | -{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm }, |
| 72 | +{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, |
72 | 73 | #endif |
73 | 74 |
|
74 | 75 | int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid); |
@@ -104,8 +105,20 @@ void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); |
104 | 105 | struct kvm_pmu { |
105 | 106 | }; |
106 | 107 |
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| 108 | +static inline int kvm_riscv_vcpu_pmu_read_legacy(struct kvm_vcpu *vcpu, unsigned int csr_num, |
| 109 | + unsigned long *val, unsigned long new_val, |
| 110 | + unsigned long wr_mask) |
| 111 | +{ |
| 112 | + if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) { |
| 113 | + *val = 0; |
| 114 | + return KVM_INSN_CONTINUE_NEXT_SEPC; |
| 115 | + } else { |
| 116 | + return KVM_INSN_ILLEGAL_TRAP; |
| 117 | + } |
| 118 | +} |
| 119 | + |
107 | 120 | #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ |
108 | | -{.base = 0, .count = 0, .func = NULL }, |
| 121 | +{.base = CSR_CYCLE, .count = 3, .func = kvm_riscv_vcpu_pmu_read_legacy }, |
109 | 122 |
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110 | 123 | static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {} |
111 | 124 | static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid) |
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