drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3

For later VBIOS versions, the fractional feedback divider is
calculated as the remainder of dividing the feedback divider by
a factor, which is set to 1000000. For reference, see:
- calculate_fb_and_fractional_fb_divider
- calc_pll_max_vco_construct

However, in case of old VBIOS versions that have
set_pixel_clock_v3, they only have 1 byte available for the
fractional feedback divider, and it's expected to be set to the
remainder from dividing the feedback divider by 10.
For reference see the legacy display code:
- amdgpu_pll_compute
- amdgpu_atombios_crtc_program_pll

This commit fixes set_pixel_clock_v3 by dividing the fractional
feedback divider passed to the function by 100000.

Fixes: 4562236 ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Timur Kristóf <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Reviewed-by: Alex Hung <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit 027e7ac)
Cc: [email protected]

Author: Timur Kristóf

drivers/gpu/drm/amd/display/dc/bios/command_table.c

@@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3(
 	allocation.sPCLKInput.usFbDiv =
 			cpu_to_le16((uint16_t)bp_params->feedback_divider);
 	allocation.sPCLKInput.ucFracFbDiv =
-			(uint8_t)bp_params->fractional_feedback_divider;
+			(uint8_t)(bp_params->fractional_feedback_divider / 100000);
 	allocation.sPCLKInput.ucPostDiv =
 			(uint8_t)bp_params->pixel_clock_post_divider;