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1 parent 5d5fc33 commit 1d20e5dCopy full SHA for 1d20e5d
arch/riscv/kernel/signal.c
@@ -84,7 +84,7 @@ static long save_v_state(struct pt_regs *regs, void __user **sc_vec)
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datap = state + 1;
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/* datap is designed to be 16 byte aligned for better performance */
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- WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16)));
+ WARN_ON(!IS_ALIGNED((unsigned long)datap, 16));
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get_cpu_vector_context();
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riscv_v_vstate_save(¤t->thread.vstate, regs);
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