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83 | 83 | #define ESDHC_TUNE_CTRL_STEP 1
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84 | 84 | #define ESDHC_TUNE_CTRL_MIN 0
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85 | 85 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
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| 86 | +#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK GENMASK(30, 16) |
86 | 87 | #define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK GENMASK(30, 24)
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87 | 88 | #define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK GENMASK(14, 8)
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88 | 89 | #define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK GENMASK(7, 4)
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@@ -1213,7 +1214,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
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1213 | 1214 | {
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1214 | 1215 | int min, max, avg, ret;
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1215 | 1216 | int win_length, target_min, target_max, target_win_length;
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1216 |
| - u32 clk_tune_ctrl_status; |
| 1217 | + u32 clk_tune_ctrl_status, temp; |
1217 | 1218 |
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1218 | 1219 | min = ESDHC_TUNE_CTRL_MIN;
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1219 | 1220 | max = ESDHC_TUNE_CTRL_MIN;
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@@ -1269,6 +1270,13 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
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1269 | 1270 | ESDHC_AUTO_TUNING_WINDOW);
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1270 | 1271 |
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1271 | 1272 | writel(clk_tune_ctrl_status, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
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| 1273 | + ret = readl_poll_timeout(host->ioaddr + ESDHC_TUNE_CTRL_STATUS, temp, |
| 1274 | + clk_tune_ctrl_status == |
| 1275 | + FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK, temp), |
| 1276 | + 1, 10); |
| 1277 | + if (ret == -ETIMEDOUT) |
| 1278 | + dev_warn(mmc_dev(host->mmc), |
| 1279 | + "clock tuning control status not set in 10us\n"); |
1272 | 1280 |
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1273 | 1281 | ret = mmc_send_tuning(host->mmc, opcode, NULL);
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1274 | 1282 | esdhc_post_tuning(host);
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