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anderssonandersson
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Merge branch '[email protected]' into clk-for-6.14
Merge the SM8750 GCC and TCSR clock bindings through topic branch, to allow merging into DeviceTree source branch as well.
2 parents 88d9dca + 8817c21 commit 4188e51

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‎Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

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See also:
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- include/dt-bindings/clock/qcom,sm8550-tcsr.h
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- include/dt-bindings/clock/qcom,sm8650-tcsr.h
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- include/dt-bindings/clock/qcom,sm8750-tcsr.h
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properties:
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compatible:
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- qcom,sar2130p-tcsr
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- qcom,sm8550-tcsr
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- qcom,sm8650-tcsr
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- qcom,sm8750-tcsr
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- qcom,x1e80100-tcsr
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- const: syscon
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‎Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on SM8750
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on SM8750
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See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
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properties:
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compatible:
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const: qcom,sm8750-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Board Always On XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source
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- description: UFS Phy Rx symbol 0 clock source
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- description: UFS Phy Rx symbol 1 clock source
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- description: UFS Phy Tx symbol 0 clock source
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- description: USB3 Phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,sm8750-gcc";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>,
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<&pcie0_phy>,
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<&ufs_mem_phy 0>,
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<&ufs_mem_phy 1>,
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<&ufs_mem_phy 2>,
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<&usb_1_qmpphy>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎include/dt-bindings/clock/qcom,sm8750-gcc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
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/* GCC clocks */
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#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
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#define GCC_BOOT_ROM_AHB_CLK 4
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#define GCC_CAM_BIST_MCLK_AHB_CLK 5
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#define GCC_CAMERA_AHB_CLK 6
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#define GCC_CAMERA_HF_AXI_CLK 7
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#define GCC_CAMERA_SF_AXI_CLK 8
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#define GCC_CAMERA_XO_CLK 9
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#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
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#define GCC_CNOC_PCIE_SF_AXI_CLK 12
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#define GCC_DDRSS_GPU_AXI_CLK 13
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#define GCC_DDRSS_PCIE_SF_QTB_CLK 14
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#define GCC_DISP_AHB_CLK 15
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#define GCC_DISP_HF_AXI_CLK 16
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#define GCC_EVA_AHB_CLK 17
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#define GCC_EVA_AXI0_CLK 18
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#define GCC_EVA_AXI0C_CLK 19
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#define GCC_EVA_XO_CLK 20
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#define GCC_GP1_CLK 21
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#define GCC_GP1_CLK_SRC 22
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#define GCC_GP2_CLK 23
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#define GCC_GP2_CLK_SRC 24
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#define GCC_GP3_CLK 25
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#define GCC_GP3_CLK_SRC 26
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#define GCC_GPLL0 27
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#define GCC_GPLL0_OUT_EVEN 28
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#define GCC_GPLL1 29
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#define GCC_GPLL4 30
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#define GCC_GPLL7 31
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#define GCC_GPLL9 32
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#define GCC_GPU_CFG_AHB_CLK 33
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#define GCC_GPU_GEMNOC_GFX_CLK 34
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#define GCC_GPU_GPLL0_CLK_SRC 35
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 36
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#define GCC_PCIE_0_AUX_CLK 37
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#define GCC_PCIE_0_AUX_CLK_SRC 38
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#define GCC_PCIE_0_CFG_AHB_CLK 39
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#define GCC_PCIE_0_MSTR_AXI_CLK 40
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#define GCC_PCIE_0_PHY_RCHNG_CLK 41
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
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#define GCC_PCIE_0_PIPE_CLK 43
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#define GCC_PCIE_0_PIPE_CLK_SRC 44
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#define GCC_PCIE_0_SLV_AXI_CLK 45
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
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#define GCC_PCIE_RSCC_CFG_AHB_CLK 47
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#define GCC_PCIE_RSCC_XO_CLK 48
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#define GCC_PDM2_CLK 49
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#define GCC_PDM2_CLK_SRC 50
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#define GCC_PDM_AHB_CLK 51
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#define GCC_PDM_XO4_CLK 52
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#define GCC_QMIP_CAMERA_CMD_AHB_CLK 53
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 54
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 55
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#define GCC_QMIP_GPU_AHB_CLK 56
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#define GCC_QMIP_PCIE_AHB_CLK 57
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#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 58
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 59
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#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 60
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 61
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#define GCC_QUPV3_I2C_CORE_CLK 62
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#define GCC_QUPV3_I2C_S0_CLK 63
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#define GCC_QUPV3_I2C_S0_CLK_SRC 64
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#define GCC_QUPV3_I2C_S1_CLK 65
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#define GCC_QUPV3_I2C_S1_CLK_SRC 66
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#define GCC_QUPV3_I2C_S2_CLK 67
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#define GCC_QUPV3_I2C_S2_CLK_SRC 68
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#define GCC_QUPV3_I2C_S3_CLK 69
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#define GCC_QUPV3_I2C_S3_CLK_SRC 70
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#define GCC_QUPV3_I2C_S4_CLK 71
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#define GCC_QUPV3_I2C_S4_CLK_SRC 72
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#define GCC_QUPV3_I2C_S5_CLK 73
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#define GCC_QUPV3_I2C_S5_CLK_SRC 74
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#define GCC_QUPV3_I2C_S6_CLK 75
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#define GCC_QUPV3_I2C_S6_CLK_SRC 76
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#define GCC_QUPV3_I2C_S7_CLK 77
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#define GCC_QUPV3_I2C_S7_CLK_SRC 78
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#define GCC_QUPV3_I2C_S8_CLK 79
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#define GCC_QUPV3_I2C_S8_CLK_SRC 80
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#define GCC_QUPV3_I2C_S9_CLK 81
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#define GCC_QUPV3_I2C_S9_CLK_SRC 82
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#define GCC_QUPV3_I2C_S_AHB_CLK 83
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
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#define GCC_QUPV3_WRAP1_CORE_CLK 85
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#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
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#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
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#define GCC_QUPV3_WRAP1_S0_CLK 88
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
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#define GCC_QUPV3_WRAP1_S1_CLK 90
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
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#define GCC_QUPV3_WRAP1_S2_CLK 92
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
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#define GCC_QUPV3_WRAP1_S3_CLK 94
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
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#define GCC_QUPV3_WRAP1_S4_CLK 96
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
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#define GCC_QUPV3_WRAP1_S5_CLK 98
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
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#define GCC_QUPV3_WRAP1_S6_CLK 100
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
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#define GCC_QUPV3_WRAP1_S7_CLK 102
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
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#define GCC_QUPV3_WRAP2_CORE_CLK 105
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#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 106
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#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 107
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#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 108
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#define GCC_QUPV3_WRAP2_S0_CLK 109
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
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#define GCC_QUPV3_WRAP2_S1_CLK 111
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
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#define GCC_QUPV3_WRAP2_S2_CLK 113
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
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#define GCC_QUPV3_WRAP2_S3_CLK 115
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
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#define GCC_QUPV3_WRAP2_S4_CLK 117
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
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#define GCC_QUPV3_WRAP2_S5_CLK 119
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
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#define GCC_QUPV3_WRAP2_S6_CLK 121
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#define GCC_QUPV3_WRAP2_S6_CLK_SRC 122
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#define GCC_QUPV3_WRAP2_S7_CLK 123
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#define GCC_QUPV3_WRAP2_S7_CLK_SRC 124
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 125
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 126
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#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 127
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#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 128
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130
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#define GCC_SDCC2_AHB_CLK 131
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#define GCC_SDCC2_APPS_CLK 132
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#define GCC_SDCC2_APPS_CLK_SRC 133
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#define GCC_SDCC4_AHB_CLK 134
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#define GCC_SDCC4_APPS_CLK 135
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#define GCC_SDCC4_APPS_CLK_SRC 136
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#define GCC_UFS_PHY_AHB_CLK 137
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#define GCC_UFS_PHY_AXI_CLK 138
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#define GCC_UFS_PHY_AXI_CLK_SRC 139
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140
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#define GCC_UFS_PHY_ICE_CORE_CLK 141
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143
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#define GCC_UFS_PHY_PHY_AUX_CLK 144
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155
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#define GCC_USB30_PRIM_MASTER_CLK 156
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 157
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160
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#define GCC_USB30_PRIM_SLEEP_CLK 161
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#define GCC_USB3_PRIM_PHY_AUX_CLK 162
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 165
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166
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#define GCC_VIDEO_AHB_CLK 167
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#define GCC_VIDEO_AXI0_CLK 168
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#define GCC_VIDEO_AXI1_CLK 169
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#define GCC_VIDEO_XO_CLK 170
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/* GCC power domains */
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#define GCC_PCIE_0_GDSC 0
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#define GCC_PCIE_0_PHY_GDSC 1
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#define GCC_UFS_MEM_PHY_GDSC 2
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#define GCC_UFS_PHY_GDSC 3
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#define GCC_USB30_PRIM_GDSC 4
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#define GCC_USB3_PHY_GDSC 5
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/* GCC resets */
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#define GCC_CAMERA_BCR 0
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#define GCC_DISPLAY_BCR 1
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#define GCC_EVA_BCR 2
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#define GCC_GPU_BCR 3
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#define GCC_PCIE_0_BCR 4
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#define GCC_PCIE_0_LINK_DOWN_BCR 5
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
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#define GCC_PCIE_0_PHY_BCR 7
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
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#define GCC_PCIE_PHY_BCR 9
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#define GCC_PCIE_PHY_CFG_AHB_BCR 10
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#define GCC_PCIE_PHY_COM_BCR 11
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#define GCC_PCIE_RSCC_BCR 12
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#define GCC_PDM_BCR 13
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#define GCC_QUPV3_WRAPPER_1_BCR 14
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#define GCC_QUPV3_WRAPPER_2_BCR 15
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#define GCC_QUPV3_WRAPPER_I2C_BCR 16
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#define GCC_QUSB2PHY_PRIM_BCR 17
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#define GCC_QUSB2PHY_SEC_BCR 18
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#define GCC_SDCC2_BCR 19
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#define GCC_SDCC4_BCR 20
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#define GCC_UFS_PHY_BCR 21
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#define GCC_USB30_PRIM_BCR 22
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#define GCC_USB3_DP_PHY_PRIM_BCR 23
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#define GCC_USB3_DP_PHY_SEC_BCR 24
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#define GCC_USB3_PHY_PRIM_BCR 25
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#define GCC_USB3_PHY_SEC_BCR 26
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#define GCC_USB3PHY_PHY_PRIM_BCR 27
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#define GCC_USB3PHY_PHY_SEC_BCR 28
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#define GCC_VIDEO_AXI0_CLK_ARES 29
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#define GCC_VIDEO_AXI1_CLK_ARES 30
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#define GCC_VIDEO_BCR 31
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#define GCC_EVA_AXI0_CLK_ARES 32
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#define GCC_EVA_AXI0C_CLK_ARES 33
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#endif

‎include/dt-bindings/clock/qcom,sm8750-tcsr.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
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#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
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/* TCSR_CC clocks */
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#define TCSR_PCIE_0_CLKREF_EN 0
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#define TCSR_UFS_CLKREF_EN 1
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#define TCSR_USB2_CLKREF_EN 2
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#define TCSR_USB3_CLKREF_EN 3
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#endif

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