Skip to content

Commit 594c8df

Browse files
zmlin1998Pratyush Yadav
authored andcommitted
mtd: spi-nor: macronix: Add fixups for MX25L3255E
SFDP of MX25L3255E is JESD216, which does not include the Quad Enable bit Requirement in BFPT. As a result, during BFPT parsing, the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable. Therefore, it is necessary to correct this setting by late_init. In addition, MX25L3255E also supports 1-4-4 page program in 3-byte address mode. However, since the 3-byte address 1-4-4 page program is not defined in SFDP, it needs to be configured in late_init. Signed-off-by: Cheng Ming Lin <[email protected]> Acked-by: Pratyush Yadav <[email protected]> Signed-off-by: Pratyush Yadav <[email protected]> [[email protected]: move params declaration to top, and use it everywhere] Link: https://lore.kernel.org/r/[email protected]
1 parent c425efa commit 594c8df

File tree

1 file changed

+30
-0
lines changed

1 file changed

+30
-0
lines changed

drivers/mtd/spi-nor/macronix.c

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
5858
return 0;
5959
}
6060

61+
static int
62+
mx25l3255e_late_init_fixups(struct spi_nor *nor)
63+
{
64+
struct spi_nor_flash_parameter *params = nor->params;
65+
66+
/*
67+
* SFDP of MX25L3255E is JESD216, which does not include the Quad
68+
* Enable bit Requirement in BFPT. As a result, during BFPT parsing,
69+
* the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
70+
* Therefore, it is necessary to correct this setting by late_init.
71+
*/
72+
params->quad_enable = spi_nor_sr1_bit6_quad_enable;
73+
74+
/*
75+
* In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
76+
* address mode. However, since the 3-byte address 1-4-4 page program
77+
* is not defined in SFDP, it needs to be configured in late_init.
78+
*/
79+
params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
80+
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_4_4],
81+
SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);
82+
83+
return 0;
84+
}
85+
6186
static const struct spi_nor_fixups mx25l25635_fixups = {
6287
.post_bfpt = mx25l25635_post_bfpt_fixups,
6388
.post_sfdp = macronix_qpp4b_post_sfdp_fixups,
@@ -67,6 +92,10 @@ static const struct spi_nor_fixups macronix_qpp4b_fixups = {
6792
.post_sfdp = macronix_qpp4b_post_sfdp_fixups,
6893
};
6994

95+
static const struct spi_nor_fixups mx25l3255e_fixups = {
96+
.late_init = mx25l3255e_late_init_fixups,
97+
};
98+
7099
static const struct flash_info macronix_nor_parts[] = {
71100
{
72101
.id = SNOR_ID(0xc2, 0x20, 0x10),
@@ -199,6 +228,7 @@ static const struct flash_info macronix_nor_parts[] = {
199228
}, {
200229
/* MX25L3255E */
201230
.id = SNOR_ID(0xc2, 0x9e, 0x16),
231+
.fixups = &mx25l3255e_fixups,
202232
},
203233
/*
204234
* This spares us of adding new flash entries for flashes that can be

0 commit comments

Comments
 (0)