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airliedairlied
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Merge tag 'amd-drm-fixes-6.11-2024-07-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-fixes-6.11-2024-07-18: amdgpu: - Bump driver version for GFX12 DCC - DC documention warning fixes - VCN unified queue power fix - SMU fix - RAS fix - Display corruption fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 412dbc6 + e3615bd commit 627a24f

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18 files changed

+246
-141
lines changed

18 files changed

+246
-141
lines changed

‎Documentation/gpu/amdgpu/display/dcn-blocks.rst

Lines changed: 6 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -8,37 +8,22 @@ and the code documentation when it is automatically generated.
88
DCHUBBUB
99
--------
1010

11-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
11+
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
1212
:doc: overview
1313

14-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
15-
:export:
16-
17-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
18-
:internal:
19-
2014
HUBP
2115
----
2216

2317
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
2418
:doc: overview
2519

26-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
27-
:export:
28-
29-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
30-
:internal:
31-
3220
DPP
3321
---
3422

35-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
23+
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
3624
:doc: overview
3725

38-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
39-
:export:
40-
41-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
26+
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
4227
:internal:
4328

4429
MPC
@@ -47,32 +32,24 @@ MPC
4732
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
4833
:doc: overview
4934

50-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
51-
:export:
52-
5335
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
5436
:internal:
37+
:no-identifiers: mpcc_blnd_cfg mpcc_alpha_blend_mode
5538

5639
OPP
5740
---
5841

5942
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
6043
:doc: overview
6144

62-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
63-
:export:
64-
6545
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
6646
:internal:
6747

6848
DIO
6949
---
7050

71-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
51+
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
7252
:doc: overview
7353

74-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
75-
:export:
76-
77-
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
54+
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
7855
:internal:

‎Documentation/gpu/amdgpu/display/display-manager.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ The DRM blend mode and its elements are then mapped by AMDGPU display manager
132132
(MPC), as follows:
133133

134134
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
135-
:functions: mpcc_blnd_cfg
135+
:identifiers: mpcc_blnd_cfg
136136

137137
Therefore, the blending configuration for a single MPCC instance on the MPC
138138
tree is defined by :c:type:`mpcc_blnd_cfg`, where
@@ -144,7 +144,7 @@ alpha and plane alpha values. It sets one of the three modes for
144144
:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
145145

146146
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
147-
:functions: mpcc_alpha_blend_mode
147+
:identifiers: mpcc_alpha_blend_mode
148148

149149
DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
150150
blend formula, as follows:

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,9 +116,10 @@
116116
* - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
117117
* - 3.56.0 - Update IB start address and size alignment for decode and encode
118118
* - 3.57.0 - Compute tunneling on GFX10+
119+
* - 3.58.0 - Add GFX12 DCC support
119120
*/
120121
#define KMS_DRIVER_MAJOR 3
121-
#define KMS_DRIVER_MINOR 57
122+
#define KMS_DRIVER_MINOR 58
122123
#define KMS_DRIVER_PATCHLEVEL 0
123124

124125
/*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 83 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1591,6 +1591,68 @@ static void psp_ras_ta_check_status(struct psp_context *psp)
15911591
}
15921592
}
15931593

1594+
static int psp_ras_send_cmd(struct psp_context *psp,
1595+
enum ras_command cmd_id, void *in, void *out)
1596+
{
1597+
struct ta_ras_shared_memory *ras_cmd;
1598+
uint32_t cmd = cmd_id;
1599+
int ret = 0;
1600+
1601+
if (!in)
1602+
return -EINVAL;
1603+
1604+
mutex_lock(&psp->ras_context.mutex);
1605+
ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1606+
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1607+
1608+
switch (cmd) {
1609+
case TA_RAS_COMMAND__ENABLE_FEATURES:
1610+
case TA_RAS_COMMAND__DISABLE_FEATURES:
1611+
memcpy(&ras_cmd->ras_in_message,
1612+
in, sizeof(ras_cmd->ras_in_message));
1613+
break;
1614+
case TA_RAS_COMMAND__TRIGGER_ERROR:
1615+
memcpy(&ras_cmd->ras_in_message.trigger_error,
1616+
in, sizeof(ras_cmd->ras_in_message.trigger_error));
1617+
break;
1618+
case TA_RAS_COMMAND__QUERY_ADDRESS:
1619+
memcpy(&ras_cmd->ras_in_message.address,
1620+
in, sizeof(ras_cmd->ras_in_message.address));
1621+
break;
1622+
default:
1623+
dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd);
1624+
ret = -EINVAL;
1625+
goto err_out;
1626+
}
1627+
1628+
ras_cmd->cmd_id = cmd;
1629+
ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1630+
1631+
switch (cmd) {
1632+
case TA_RAS_COMMAND__TRIGGER_ERROR:
1633+
if (ret || psp->cmd_buf_mem->resp.status)
1634+
ret = -EINVAL;
1635+
else if (out)
1636+
memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status));
1637+
break;
1638+
case TA_RAS_COMMAND__QUERY_ADDRESS:
1639+
if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status)
1640+
ret = -EINVAL;
1641+
else if (out)
1642+
memcpy(out,
1643+
&ras_cmd->ras_out_message.address,
1644+
sizeof(ras_cmd->ras_out_message.address));
1645+
break;
1646+
default:
1647+
break;
1648+
}
1649+
1650+
err_out:
1651+
mutex_unlock(&psp->ras_context.mutex);
1652+
1653+
return ret;
1654+
}
1655+
15941656
int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
15951657
{
15961658
struct ta_ras_shared_memory *ras_cmd;
@@ -1632,23 +1694,15 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
16321694
int psp_ras_enable_features(struct psp_context *psp,
16331695
union ta_ras_cmd_input *info, bool enable)
16341696
{
1635-
struct ta_ras_shared_memory *ras_cmd;
1697+
enum ras_command cmd_id;
16361698
int ret;
16371699

1638-
if (!psp->ras_context.context.initialized)
1700+
if (!psp->ras_context.context.initialized || !info)
16391701
return -EINVAL;
16401702

1641-
ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1642-
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1643-
1644-
if (enable)
1645-
ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1646-
else
1647-
ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1648-
1649-
ras_cmd->ras_in_message = *info;
1650-
1651-
ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1703+
cmd_id = enable ?
1704+
TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES;
1705+
ret = psp_ras_send_cmd(psp, cmd_id, info, NULL);
16521706
if (ret)
16531707
return -EINVAL;
16541708

@@ -1672,6 +1726,8 @@ int psp_ras_terminate(struct psp_context *psp)
16721726

16731727
psp->ras_context.context.initialized = false;
16741728

1729+
mutex_destroy(&psp->ras_context.mutex);
1730+
16751731
return ret;
16761732
}
16771733

@@ -1756,9 +1812,10 @@ int psp_ras_initialize(struct psp_context *psp)
17561812

17571813
ret = psp_ta_load(psp, &psp->ras_context.context);
17581814

1759-
if (!ret && !ras_cmd->ras_status)
1815+
if (!ret && !ras_cmd->ras_status) {
17601816
psp->ras_context.context.initialized = true;
1761-
else {
1817+
mutex_init(&psp->ras_context.mutex);
1818+
} else {
17621819
if (ras_cmd->ras_status)
17631820
dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
17641821

@@ -1772,12 +1829,12 @@ int psp_ras_initialize(struct psp_context *psp)
17721829
int psp_ras_trigger_error(struct psp_context *psp,
17731830
struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
17741831
{
1775-
struct ta_ras_shared_memory *ras_cmd;
17761832
struct amdgpu_device *adev = psp->adev;
17771833
int ret;
17781834
uint32_t dev_mask;
1835+
uint32_t ras_status = 0;
17791836

1780-
if (!psp->ras_context.context.initialized)
1837+
if (!psp->ras_context.context.initialized || !info)
17811838
return -EINVAL;
17821839

17831840
switch (info->block_id) {
@@ -1801,13 +1858,8 @@ int psp_ras_trigger_error(struct psp_context *psp,
18011858
dev_mask &= AMDGPU_RAS_INST_MASK;
18021859
info->sub_block_index |= dev_mask;
18031860

1804-
ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1805-
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1806-
1807-
ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1808-
ras_cmd->ras_in_message.trigger_error = *info;
1809-
1810-
ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1861+
ret = psp_ras_send_cmd(psp,
1862+
TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status);
18111863
if (ret)
18121864
return -EINVAL;
18131865

@@ -1817,9 +1869,9 @@ int psp_ras_trigger_error(struct psp_context *psp,
18171869
if (amdgpu_ras_intr_triggered())
18181870
return 0;
18191871

1820-
if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1872+
if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
18211873
return -EACCES;
1822-
else if (ras_cmd->ras_status)
1874+
else if (ras_status)
18231875
return -EINVAL;
18241876

18251877
return 0;
@@ -1829,25 +1881,16 @@ int psp_ras_query_address(struct psp_context *psp,
18291881
struct ta_ras_query_address_input *addr_in,
18301882
struct ta_ras_query_address_output *addr_out)
18311883
{
1832-
struct ta_ras_shared_memory *ras_cmd;
18331884
int ret;
18341885

1835-
if (!psp->ras_context.context.initialized)
1836-
return -EINVAL;
1837-
1838-
ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1839-
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1840-
1841-
ras_cmd->cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS;
1842-
ras_cmd->ras_in_message.address = *addr_in;
1843-
1844-
ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1845-
if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status)
1886+
if (!psp->ras_context.context.initialized ||
1887+
!addr_in || !addr_out)
18461888
return -EINVAL;
18471889

1848-
*addr_out = ras_cmd->ras_out_message.address;
1890+
ret = psp_ras_send_cmd(psp,
1891+
TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out);
18491892

1850-
return 0;
1893+
return ret;
18511894
}
18521895
// ras end
18531896

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,7 @@ struct psp_xgmi_context {
200200
struct psp_ras_context {
201201
struct ta_context context;
202202
struct amdgpu_ras *ras;
203+
struct mutex mutex;
203204
};
204205

205206
#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size
348348

349349
context->session_id = ta_id;
350350

351+
mutex_lock(&psp->ras_context.mutex);
351352
ret = prep_ta_mem_context(&context->mem_context, shared_buf, shared_buf_len);
352353
if (ret)
353354
goto err_free_shared_buf;
@@ -366,6 +367,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size
366367
ret = -EFAULT;
367368

368369
err_free_shared_buf:
370+
mutex_unlock(&psp->ras_context.mutex);
369371
kfree(shared_buf);
370372

371373
return ret;

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