Skip to content

Commit 920e6bf

Browse files
Axe Yangstorulf
authored andcommitted
mmc: mtk-sd: Add condition to enable 'single' burst type
This change add a condition for 'single' burst type selection. Read AXI_LEN field from EMMC50_CFG2(AHB2AXI wrapper) register, if the value is not 0, it means the HWIP is using AXI as AMBA bus, which do not support 'single' burst type. Suggested-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Axe Yang <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
1 parent 1c73875 commit 920e6bf

File tree

1 file changed

+12
-4
lines changed

1 file changed

+12
-4
lines changed

drivers/mmc/host/mtk-sd.c

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,7 @@
8484
#define EMMC51_CFG0 0x204
8585
#define EMMC50_CFG0 0x208
8686
#define EMMC50_CFG1 0x20c
87+
#define EMMC50_CFG2 0x21c
8788
#define EMMC50_CFG3 0x220
8889
#define SDC_FIFO_CFG 0x228
8990
#define CQHCI_SETTING 0x7fc
@@ -306,7 +307,10 @@
306307
/* EMMC50_CFG1 mask */
307308
#define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
308309

309-
#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
310+
/* EMMC50_CFG2 mask */
311+
#define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */
312+
313+
#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
310314

311315
#define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
312316
#define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
@@ -1917,9 +1921,13 @@ static void msdc_init_hw(struct msdc_host *host)
19171921
pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
19181922
pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
19191923

1920-
/* Set single burst mode, auto sync state clear, block gap stop clk */
1921-
pb1_val |= MSDC_PB1_SINGLE_BURST | MSDC_PB1_RSVD20 |
1922-
MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
1924+
/* Support 'single' burst type only when AXI_LEN is 0 */
1925+
sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
1926+
if (!val)
1927+
pb1_val |= MSDC_PB1_SINGLE_BURST;
1928+
1929+
/* Set auto sync state clear, block gap stop clk */
1930+
pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
19231931

19241932
/* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
19251933
pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |

0 commit comments

Comments
 (0)