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84 | 84 | #define EMMC51_CFG0 0x204
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85 | 85 | #define EMMC50_CFG0 0x208
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86 | 86 | #define EMMC50_CFG1 0x20c
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| 87 | +#define EMMC50_CFG2 0x21c |
87 | 88 | #define EMMC50_CFG3 0x220
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88 | 89 | #define SDC_FIFO_CFG 0x228
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89 | 90 | #define CQHCI_SETTING 0x7fc
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306 | 307 | /* EMMC50_CFG1 mask */
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307 | 308 | #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
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308 | 309 |
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309 |
| -#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ |
| 310 | +/* EMMC50_CFG2 mask */ |
| 311 | +#define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */ |
| 312 | + |
| 313 | +#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ |
310 | 314 |
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311 | 315 | #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
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312 | 316 | #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
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@@ -1917,9 +1921,13 @@ static void msdc_init_hw(struct msdc_host *host)
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1917 | 1921 | pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
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1918 | 1922 | pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
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1919 | 1923 |
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1920 |
| - /* Set single burst mode, auto sync state clear, block gap stop clk */ |
1921 |
| - pb1_val |= MSDC_PB1_SINGLE_BURST | MSDC_PB1_RSVD20 | |
1922 |
| - MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER; |
| 1924 | + /* Support 'single' burst type only when AXI_LEN is 0 */ |
| 1925 | + sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val); |
| 1926 | + if (!val) |
| 1927 | + pb1_val |= MSDC_PB1_SINGLE_BURST; |
| 1928 | + |
| 1929 | + /* Set auto sync state clear, block gap stop clk */ |
| 1930 | + pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER; |
1923 | 1931 |
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1924 | 1932 | /* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
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1925 | 1933 | pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |
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