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MIPS: mobileye: eyeq5: add OLB system-controller node
The OLB ("Other Logic Block") is a system-controller region hosting clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Remove fixed-clocks previously used; replace references. Add parent crystal clock, fixed at 30MHz. Add pin nodes for all functions. Add mobileye,eyeq5-olb compatible node, hosting clk, reset and pinctrl. Add reset and pinctrl references to UART nodes. Signed-off-by: Théo Lebrun <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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‎arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi renamed to ‎arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi

Lines changed: 16 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -3,42 +3,20 @@
33
* Copyright 2023 Mobileye Vision Technologies Ltd.
44
*/
55

6+
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
7+
68
/ {
79
/* Fixed clock */
8-
pll_cpu: pll-cpu {
9-
compatible = "fixed-clock";
10-
#clock-cells = <0>;
11-
clock-frequency = <1500000000>;
12-
};
13-
14-
pll_vdi: pll-vdi {
15-
compatible = "fixed-clock";
16-
#clock-cells = <0>;
17-
clock-frequency = <1280000000>;
18-
};
19-
20-
pll_per: pll-per {
21-
compatible = "fixed-clock";
22-
#clock-cells = <0>;
23-
clock-frequency = <2000000000>;
24-
};
25-
26-
pll_ddr0: pll-ddr0 {
27-
compatible = "fixed-clock";
28-
#clock-cells = <0>;
29-
clock-frequency = <1857210000>;
30-
};
31-
32-
pll_ddr1: pll-ddr1 {
10+
xtal: xtal {
3311
compatible = "fixed-clock";
3412
#clock-cells = <0>;
35-
clock-frequency = <1857210000>;
13+
clock-frequency = <30000000>;
3614
};
3715

3816
/* PLL_CPU derivatives */
3917
occ_cpu: occ-cpu {
4018
compatible = "fixed-factor-clock";
41-
clocks = <&pll_cpu>;
19+
clocks = <&olb EQ5C_PLL_CPU>;
4220
#clock-cells = <0>;
4321
clock-div = <1>;
4422
clock-mult = <1>;
@@ -101,7 +79,7 @@
10179
};
10280
occ_isram: occ-isram {
10381
compatible = "fixed-factor-clock";
104-
clocks = <&pll_cpu>;
82+
clocks = <&olb EQ5C_PLL_CPU>;
10583
#clock-cells = <0>;
10684
clock-div = <2>;
10785
clock-mult = <1>;
@@ -115,7 +93,7 @@
11593
};
11694
occ_dbu: occ-dbu {
11795
compatible = "fixed-factor-clock";
118-
clocks = <&pll_cpu>;
96+
clocks = <&olb EQ5C_PLL_CPU>;
11997
#clock-cells = <0>;
12098
clock-div = <10>;
12199
clock-mult = <1>;
@@ -130,7 +108,7 @@
130108
/* PLL_VDI derivatives */
131109
occ_vdi: occ-vdi {
132110
compatible = "fixed-factor-clock";
133-
clocks = <&pll_vdi>;
111+
clocks = <&olb EQ5C_PLL_VDI>;
134112
#clock-cells = <0>;
135113
clock-div = <2>;
136114
clock-mult = <1>;
@@ -144,7 +122,7 @@
144122
};
145123
occ_can_ser: occ-can-ser {
146124
compatible = "fixed-factor-clock";
147-
clocks = <&pll_vdi>;
125+
clocks = <&olb EQ5C_PLL_VDI>;
148126
#clock-cells = <0>;
149127
clock-div = <16>;
150128
clock-mult = <1>;
@@ -158,15 +136,15 @@
158136
};
159137
i2c_ser_clk: i2c-ser-clk {
160138
compatible = "fixed-factor-clock";
161-
clocks = <&pll_vdi>;
139+
clocks = <&olb EQ5C_PLL_VDI>;
162140
#clock-cells = <0>;
163141
clock-div = <20>;
164142
clock-mult = <1>;
165143
};
166144
/* PLL_PER derivatives */
167145
occ_periph: occ-periph {
168146
compatible = "fixed-factor-clock";
169-
clocks = <&pll_per>;
147+
clocks = <&olb EQ5C_PLL_PER>;
170148
#clock-cells = <0>;
171149
clock-div = <16>;
172150
clock-mult = <1>;
@@ -225,23 +203,23 @@
225203
};
226204
emmc_sys_clk: emmc-sys-clk {
227205
compatible = "fixed-factor-clock";
228-
clocks = <&pll_per>;
206+
clocks = <&olb EQ5C_PLL_PER>;
229207
#clock-cells = <0>;
230208
clock-div = <10>;
231209
clock-mult = <1>;
232210
clock-output-names = "emmc_sys_clk";
233211
};
234212
ccf_ctrl_clk: ccf-ctrl-clk {
235213
compatible = "fixed-factor-clock";
236-
clocks = <&pll_per>;
214+
clocks = <&olb EQ5C_PLL_PER>;
237215
#clock-cells = <0>;
238216
clock-div = <4>;
239217
clock-mult = <1>;
240218
clock-output-names = "ccf_ctrl_clk";
241219
};
242220
occ_mjpeg_core: occ-mjpeg-core {
243221
compatible = "fixed-factor-clock";
244-
clocks = <&pll_per>;
222+
clocks = <&olb EQ5C_PLL_PER>;
245223
#clock-cells = <0>;
246224
clock-div = <2>;
247225
clock-mult = <1>;
@@ -265,15 +243,15 @@
265243
};
266244
fcmu_a_clk: fcmu-a-clk {
267245
compatible = "fixed-factor-clock";
268-
clocks = <&pll_per>;
246+
clocks = <&olb EQ5C_PLL_PER>;
269247
#clock-cells = <0>;
270248
clock-div = <20>;
271249
clock-mult = <1>;
272250
clock-output-names = "fcmu_a_clk";
273251
};
274252
occ_pci_sys: occ-pci-sys {
275253
compatible = "fixed-factor-clock";
276-
clocks = <&pll_per>;
254+
clocks = <&olb EQ5C_PLL_PER>;
277255
#clock-cells = <0>;
278256
clock-div = <8>;
279257
clock-mult = <1>;

‎arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
3+
/*
4+
* Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
5+
* pin configuration node per function.
6+
*/
7+
8+
&olb {
9+
timer0_pins: timer0-pins {
10+
function = "timer0";
11+
pins = "PA0", "PA1";
12+
};
13+
timer1_pins: timer1-pins {
14+
function = "timer1";
15+
pins = "PA2", "PA3";
16+
};
17+
timer2_pins: timer2-pins {
18+
function = "timer2";
19+
pins = "PA4", "PA5";
20+
};
21+
pps0_pins: pps0-pin {
22+
function = "timer2";
23+
pins = "PA4";
24+
};
25+
pps1_pins: pps1-pin {
26+
function = "timer2";
27+
pins = "PA5";
28+
};
29+
timer5_ext_pins: timer5-ext-pins {
30+
function = "timer5";
31+
pins = "PA6", "PA7", "PA8", "PA9";
32+
};
33+
timer5_ext_input_pins: timer5-ext-input-pins {
34+
function = "timer5";
35+
pins = "PA6", "PA7";
36+
};
37+
timer5_ext_incap_a_pins: timer5-ext-incap-a-pin {
38+
function = "timer5";
39+
pins = "PA6";
40+
};
41+
timer5_ext_incap_b_pins: timer5-ext-incap-b-pin {
42+
function = "timer5";
43+
pins = "PA7";
44+
};
45+
can0_pins: can0-pins {
46+
function = "can0";
47+
pins = "PA14", "PA15";
48+
};
49+
can1_pins: can1-pins {
50+
function = "can1";
51+
pins = "PA16", "PA17";
52+
};
53+
uart0_pins: uart0-pins {
54+
function = "uart0";
55+
pins = "PA10", "PA11";
56+
};
57+
uart1_pins: uart1-pins {
58+
function = "uart1";
59+
pins = "PA12", "PA13";
60+
};
61+
spi0_pins: spi0-pins {
62+
function = "spi0";
63+
pins = "PA18", "PA19", "PA20", "PA21", "PA22";
64+
};
65+
spi1_pins: spi1-pins {
66+
function = "spi1";
67+
pins = "PA23", "PA24", "PA25", "PA26", "PA27";
68+
};
69+
spi1_slave_pins: spi1-slave-pins {
70+
function = "spi1";
71+
pins = "PA24", "PA25", "PA26";
72+
};
73+
refclk0_pins: refclk0-pin {
74+
function = "refclk0";
75+
pins = "PA28";
76+
};
77+
timer3_pins: timer3-pins {
78+
function = "timer3";
79+
pins = "PB0", "PB1";
80+
};
81+
timer4_pins: timer4-pins {
82+
function = "timer4";
83+
pins = "PB2", "PB3";
84+
};
85+
timer6_ext_pins: timer6-ext-pins {
86+
function = "timer6";
87+
pins = "PB4", "PB5", "PB6", "PB7";
88+
};
89+
timer6_ext_input_pins: timer6-ext-input-pins {
90+
function = "timer6";
91+
pins = "PB4", "PB5";
92+
};
93+
timer6_ext_incap_a_pins: timer6-ext-incap-a-pin {
94+
function = "timer6";
95+
pins = "PB4";
96+
};
97+
timer6_ext_incap_b_pins: timer6-ext-incap-b-pin {
98+
function = "timer6";
99+
pins = "PB5";
100+
};
101+
can2_pins: can2-pins {
102+
function = "can2";
103+
pins = "PB10", "PB11";
104+
};
105+
uart2_pins: uart2-pins {
106+
function = "uart2";
107+
pins = "PB8", "PB9";
108+
};
109+
spi2_pins: spi2-pins {
110+
function = "spi2";
111+
pins = "PB12", "PB13", "PB14", "PB15", "PB16";
112+
};
113+
spi3_pins: spi3-pins {
114+
function = "spi3";
115+
pins = "PB17", "PB18", "PB19", "PB20", "PB21";
116+
};
117+
spi3_slave_pins: spi3-slave-pins {
118+
function = "spi3";
119+
pins = "PB18", "PB19", "PB20";
120+
};
121+
mclk0_pins: mclk0-pin {
122+
function = "mclk0";
123+
pins = "PB22";
124+
};
125+
};

‎arch/mips/boot/dts/mobileye/eyeq5.dtsi

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55

66
#include <dt-bindings/interrupt-controller/mips-gic.h>
77

8-
#include "eyeq5-fixed-clocks.dtsi"
8+
#include "eyeq5-clocks.dtsi"
99

1010
/ {
1111
#address-cells = <2>;
@@ -78,6 +78,9 @@
7878
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
7979
clocks = <&uart_clk>, <&occ_periph>;
8080
clock-names = "uartclk", "apb_pclk";
81+
resets = <&olb 0 10>;
82+
pinctrl-names = "default";
83+
pinctrl-0 = <&uart0_pins>;
8184
};
8285

8386
uart1: serial@900000 {
@@ -88,6 +91,9 @@
8891
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
8992
clocks = <&uart_clk>, <&occ_periph>;
9093
clock-names = "uartclk", "apb_pclk";
94+
resets = <&olb 0 11>;
95+
pinctrl-names = "default";
96+
pinctrl-0 = <&uart1_pins>;
9197
};
9298

9399
uart2: serial@a00000 {
@@ -98,6 +104,18 @@
98104
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
99105
clocks = <&uart_clk>, <&occ_periph>;
100106
clock-names = "uartclk", "apb_pclk";
107+
resets = <&olb 0 12>;
108+
pinctrl-names = "default";
109+
pinctrl-0 = <&uart2_pins>;
110+
};
111+
112+
olb: system-controller@e00000 {
113+
compatible = "mobileye,eyeq5-olb", "syscon";
114+
reg = <0 0xe00000 0x0 0x400>;
115+
#reset-cells = <2>;
116+
#clock-cells = <1>;
117+
clocks = <&xtal>;
118+
clock-names = "ref";
101119
};
102120

103121
gic: interrupt-controller@140000 {
@@ -122,3 +140,5 @@
122140
};
123141
};
124142
};
143+
144+
#include "eyeq5-pins.dtsi"

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