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#define REG_PCIE1_MEM_MASK 0x0c
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#define REG_PCIE2_MEM 0x10
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#define REG_PCIE2_MEM_MASK 0x14
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- #define REG_PCIE_RESET_OPEN_DRAIN 0x018c
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- #define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
@@ -85,8 +83,7 @@ struct en_clk_soc_data {
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const u16 * idx_map ;
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u16 idx_map_nr ;
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} reset ;
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- int (* hw_init )(struct platform_device * pdev , void __iomem * base ,
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- void __iomem * np_base );
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+ int (* hw_init )(struct platform_device * pdev , void __iomem * np_base );
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};
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static const u32 gsw_base [] = { 400000000 , 500000000 };
@@ -411,7 +408,6 @@ static void en7581_pci_disable(struct clk_hw *hw)
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}
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static int en7581_clk_hw_init (struct platform_device * pdev ,
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- void __iomem * base ,
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void __iomem * np_base )
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{
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void __iomem * pb_base ;
@@ -434,10 +430,6 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
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writel (0x28000000 , pb_base + REG_PCIE2_MEM );
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writel (0xfc000000 , pb_base + REG_PCIE2_MEM_MASK );
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- val = readl (base + REG_PCIE_RESET_OPEN_DRAIN );
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- writel (val | REG_PCIE_RESET_OPEN_DRAIN_MASK ,
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- base + REG_PCIE_RESET_OPEN_DRAIN );
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-
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return 0 ;
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}
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@@ -577,7 +569,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
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soc_data = device_get_match_data (& pdev -> dev );
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if (soc_data -> hw_init ) {
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- r = soc_data -> hw_init (pdev , base , np_base );
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+ r = soc_data -> hw_init (pdev , np_base );
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if (r )
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return r ;
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}
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