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#define QCLR_PCE BIT(1)
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#define QCLR_INT BIT(0)
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+ #define QEPSTS_UPEVNT BIT(7)
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+ #define QEPSTS_FDF BIT(6)
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+ #define QEPSTS_QDF BIT(5)
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+ #define QEPSTS_QDLF BIT(4)
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+ #define QEPSTS_COEF BIT(3)
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+ #define QEPSTS_CDEF BIT(2)
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+ #define QEPSTS_FIMF BIT(1)
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+ #define QEPSTS_PCEF BIT(0)
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+
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/* EQEP Inputs */
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enum {
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TI_EQEP_SIGNAL_QEPA , /* QEPA/XCLK */
@@ -286,6 +295,9 @@ static int ti_eqep_events_configure(struct counter_device *counter)
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case COUNTER_EVENT_UNDERFLOW :
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qeint |= QEINT_PCU ;
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break ;
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+ case COUNTER_EVENT_DIRECTION_CHANGE :
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+ qeint |= QEINT_QDC ;
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+ break ;
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}
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}
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@@ -298,6 +310,7 @@ static int ti_eqep_watch_validate(struct counter_device *counter,
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switch (watch -> event ) {
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case COUNTER_EVENT_OVERFLOW :
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case COUNTER_EVENT_UNDERFLOW :
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+ case COUNTER_EVENT_DIRECTION_CHANGE :
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if (watch -> channel != 0 )
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return - EINVAL ;
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@@ -368,11 +381,27 @@ static int ti_eqep_position_enable_write(struct counter_device *counter,
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return 0 ;
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}
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+ static int ti_eqep_direction_read (struct counter_device * counter ,
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+ struct counter_count * count ,
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+ enum counter_count_direction * direction )
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+ {
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+ struct ti_eqep_cnt * priv = counter_priv (counter );
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+ u32 qepsts ;
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+
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+ regmap_read (priv -> regmap16 , QEPSTS , & qepsts );
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+
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+ * direction = (qepsts & QEPSTS_QDF ) ? COUNTER_COUNT_DIRECTION_FORWARD
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+ : COUNTER_COUNT_DIRECTION_BACKWARD ;
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+
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+ return 0 ;
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+ }
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+
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static struct counter_comp ti_eqep_position_ext [] = {
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COUNTER_COMP_CEILING (ti_eqep_position_ceiling_read ,
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ti_eqep_position_ceiling_write ),
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COUNTER_COMP_ENABLE (ti_eqep_position_enable_read ,
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ti_eqep_position_enable_write ),
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+ COUNTER_COMP_DIRECTION (ti_eqep_direction_read ),
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};
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static struct counter_signal ti_eqep_signals [] = {
@@ -439,6 +468,9 @@ static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id)
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if (qflg & QFLG_PCU )
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counter_push_event (counter , COUNTER_EVENT_UNDERFLOW , 0 );
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+ if (qflg & QFLG_QDC )
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+ counter_push_event (counter , COUNTER_EVENT_DIRECTION_CHANGE , 0 );
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+
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regmap_write (priv -> regmap16 , QCLR , qflg );
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return IRQ_HANDLED ;
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