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Taniya Dasandersson
Taniya Das
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andersson
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clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks
The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-1-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <[email protected]>
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‎drivers/clk/qcom/gcc-sa8775p.c

Lines changed: 2 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,12 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2023, Linaro Limited
55
*/
66

7-
#include <linux/clk.h>
87
#include <linux/clk-provider.h>
9-
#include <linux/err.h>
10-
#include <linux/kernel.h>
118
#include <linux/module.h>
9+
#include <linux/mod_devicetable.h>
1210
#include <linux/of.h>
1311
#include <linux/platform_device.h>
1412
#include <linux/regmap.h>
@@ -1737,26 +1735,6 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
17371735
},
17381736
};
17391737

1740-
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1741-
.halt_reg = 0x830d4,
1742-
.halt_check = BRANCH_HALT_VOTED,
1743-
.hwcg_reg = 0x830d4,
1744-
.hwcg_bit = 1,
1745-
.clkr = {
1746-
.enable_reg = 0x830d4,
1747-
.enable_mask = BIT(1),
1748-
.hw.init = &(const struct clk_init_data){
1749-
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1750-
.parent_hws = (const struct clk_hw*[]){
1751-
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1752-
},
1753-
.num_parents = 1,
1754-
.flags = CLK_SET_RATE_PARENT,
1755-
.ops = &clk_branch2_ops,
1756-
},
1757-
},
1758-
};
1759-
17601738
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
17611739
.halt_reg = 0x1c05c,
17621740
.halt_check = BRANCH_HALT_VOTED,
@@ -3809,26 +3787,6 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
38093787
},
38103788
};
38113789

3812-
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3813-
.halt_reg = 0x83018,
3814-
.halt_check = BRANCH_HALT_VOTED,
3815-
.hwcg_reg = 0x83018,
3816-
.hwcg_bit = 1,
3817-
.clkr = {
3818-
.enable_reg = 0x83018,
3819-
.enable_mask = BIT(1),
3820-
.hw.init = &(const struct clk_init_data){
3821-
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3822-
.parent_hws = (const struct clk_hw*[]){
3823-
&gcc_ufs_phy_axi_clk_src.clkr.hw,
3824-
},
3825-
.num_parents = 1,
3826-
.flags = CLK_SET_RATE_PARENT,
3827-
.ops = &clk_branch2_ops,
3828-
},
3829-
},
3830-
};
3831-
38323790
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
38333791
.halt_reg = 0x8306c,
38343792
.halt_check = BRANCH_HALT_VOTED,
@@ -3849,26 +3807,6 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
38493807
},
38503808
};
38513809

3852-
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3853-
.halt_reg = 0x8306c,
3854-
.halt_check = BRANCH_HALT_VOTED,
3855-
.hwcg_reg = 0x8306c,
3856-
.hwcg_bit = 1,
3857-
.clkr = {
3858-
.enable_reg = 0x8306c,
3859-
.enable_mask = BIT(1),
3860-
.hw.init = &(const struct clk_init_data){
3861-
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3862-
.parent_hws = (const struct clk_hw*[]){
3863-
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3864-
},
3865-
.num_parents = 1,
3866-
.flags = CLK_SET_RATE_PARENT,
3867-
.ops = &clk_branch2_ops,
3868-
},
3869-
},
3870-
};
3871-
38723810
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
38733811
.halt_reg = 0x830a4,
38743812
.halt_check = BRANCH_HALT_VOTED,
@@ -3889,26 +3827,6 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
38893827
},
38903828
};
38913829

3892-
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3893-
.halt_reg = 0x830a4,
3894-
.halt_check = BRANCH_HALT_VOTED,
3895-
.hwcg_reg = 0x830a4,
3896-
.hwcg_bit = 1,
3897-
.clkr = {
3898-
.enable_reg = 0x830a4,
3899-
.enable_mask = BIT(1),
3900-
.hw.init = &(const struct clk_init_data){
3901-
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3902-
.parent_hws = (const struct clk_hw*[]){
3903-
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3904-
},
3905-
.num_parents = 1,
3906-
.flags = CLK_SET_RATE_PARENT,
3907-
.ops = &clk_branch2_ops,
3908-
},
3909-
},
3910-
};
3911-
39123830
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
39133831
.halt_reg = 0x83028,
39143832
.halt_check = BRANCH_HALT_DELAY,
@@ -3983,26 +3901,6 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
39833901
},
39843902
};
39853903

3986-
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3987-
.halt_reg = 0x83064,
3988-
.halt_check = BRANCH_HALT_VOTED,
3989-
.hwcg_reg = 0x83064,
3990-
.hwcg_bit = 1,
3991-
.clkr = {
3992-
.enable_reg = 0x83064,
3993-
.enable_mask = BIT(1),
3994-
.hw.init = &(const struct clk_init_data){
3995-
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3996-
.parent_hws = (const struct clk_hw*[]){
3997-
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3998-
},
3999-
.num_parents = 1,
4000-
.flags = CLK_SET_RATE_PARENT,
4001-
.ops = &clk_branch2_ops,
4002-
},
4003-
},
4004-
};
4005-
40063904
static struct clk_branch gcc_usb20_master_clk = {
40073905
.halt_reg = 0x1c018,
40083906
.halt_check = BRANCH_HALT,
@@ -4379,7 +4277,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
43794277
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
43804278
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
43814279
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4382-
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
43834280
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
43844281
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
43854282
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
@@ -4569,13 +4466,10 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
45694466
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
45704467
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
45714468
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4572-
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
45734469
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
45744470
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4575-
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
45764471
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
45774472
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4578-
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
45794473
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
45804474
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
45814475
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
@@ -4584,7 +4478,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
45844478
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
45854479
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
45864480
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4587-
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
45884481
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
45894482
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
45904483
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,

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