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Marc Zyngier
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KVM: arm64: Add selftest checking how the absence of GICv3 is handled
Given how tortuous and fragile the whole lack-of-GICv3 story is, add a selftest checking that we don't regress it. Reviewed-by: Oliver Upton <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]>
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‎tools/testing/selftests/kvm/Makefile

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@@ -163,6 +163,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/vgic_init
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TEST_GEN_PROGS_aarch64 += aarch64/vgic_irq
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TEST_GEN_PROGS_aarch64 += aarch64/vgic_lpi_stress
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TEST_GEN_PROGS_aarch64 += aarch64/vpmu_counter_access
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TEST_GEN_PROGS_aarch64 += aarch64/no-vgic-v3
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TEST_GEN_PROGS_aarch64 += access_tracking_perf_test
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TEST_GEN_PROGS_aarch64 += arch_timer
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TEST_GEN_PROGS_aarch64 += demand_paging_test

‎tools/testing/selftests/kvm/aarch64/no-vgic-v3.c

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// SPDX-License-Identifier: GPL-2.0
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// Check that, on a GICv3 system, not configuring GICv3 correctly
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// results in all of the sysregs generating an UNDEF exception.
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#include <test_util.h>
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#include <kvm_util.h>
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#include <processor.h>
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static volatile bool handled;
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#define __check_sr_read(r) \
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({ \
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uint64_t val; \
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\
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handled = false; \
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dsb(sy); \
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val = read_sysreg_s(SYS_ ## r); \
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val; \
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})
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#define __check_sr_write(r) \
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do { \
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handled = false; \
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dsb(sy); \
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write_sysreg_s(0, SYS_ ## r); \
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isb(); \
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} while(0)
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/* Fatal checks */
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#define check_sr_read(r) \
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do { \
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__check_sr_read(r); \
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__GUEST_ASSERT(handled, #r " no read trap"); \
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} while(0)
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#define check_sr_write(r) \
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do { \
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__check_sr_write(r); \
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__GUEST_ASSERT(handled, #r " no write trap"); \
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} while(0)
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#define check_sr_rw(r) \
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do { \
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check_sr_read(r); \
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check_sr_write(r); \
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} while(0)
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static void guest_code(void)
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{
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uint64_t val;
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/*
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* Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having
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* hidden the feature at runtime without any other userspace action.
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*/
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__GUEST_ASSERT(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC),
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read_sysreg(id_aa64pfr0_el1)) == 0,
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"GICv3 wrongly advertised");
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/*
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* Access all GICv3 registers, and fail if we don't get an UNDEF.
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* Note that we happily access all the APxRn registers without
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* checking their existance, as all we want to see is a failure.
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*/
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check_sr_rw(ICC_PMR_EL1);
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check_sr_read(ICC_IAR0_EL1);
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check_sr_write(ICC_EOIR0_EL1);
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check_sr_rw(ICC_HPPIR0_EL1);
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check_sr_rw(ICC_BPR0_EL1);
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check_sr_rw(ICC_AP0R0_EL1);
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check_sr_rw(ICC_AP0R1_EL1);
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check_sr_rw(ICC_AP0R2_EL1);
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check_sr_rw(ICC_AP0R3_EL1);
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check_sr_rw(ICC_AP1R0_EL1);
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check_sr_rw(ICC_AP1R1_EL1);
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check_sr_rw(ICC_AP1R2_EL1);
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check_sr_rw(ICC_AP1R3_EL1);
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check_sr_write(ICC_DIR_EL1);
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check_sr_read(ICC_RPR_EL1);
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check_sr_write(ICC_SGI1R_EL1);
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check_sr_write(ICC_ASGI1R_EL1);
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check_sr_write(ICC_SGI0R_EL1);
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check_sr_read(ICC_IAR1_EL1);
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check_sr_write(ICC_EOIR1_EL1);
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check_sr_rw(ICC_HPPIR1_EL1);
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check_sr_rw(ICC_BPR1_EL1);
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check_sr_rw(ICC_CTLR_EL1);
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check_sr_rw(ICC_IGRPEN0_EL1);
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check_sr_rw(ICC_IGRPEN1_EL1);
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/*
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* ICC_SRE_EL1 may not be trappable, as ICC_SRE_EL2.Enable can
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* be RAO/WI. Engage in non-fatal accesses, starting with a
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* write of 0 to try and disable SRE, and let's see if it
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* sticks.
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*/
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__check_sr_write(ICC_SRE_EL1);
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if (!handled)
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GUEST_PRINTF("ICC_SRE_EL1 write not trapping (OK)\n");
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val = __check_sr_read(ICC_SRE_EL1);
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if (!handled) {
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__GUEST_ASSERT((val & BIT(0)),
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"ICC_SRE_EL1 not trapped but ICC_SRE_EL1.SRE not set\n");
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GUEST_PRINTF("ICC_SRE_EL1 read not trapping (OK)\n");
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}
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GUEST_DONE();
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}
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static void guest_undef_handler(struct ex_regs *regs)
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{
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/* Success, we've gracefully exploded! */
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handled = true;
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regs->pc += 4;
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}
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static void test_run_vcpu(struct kvm_vcpu *vcpu)
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{
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struct ucall uc;
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do {
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vcpu_run(vcpu);
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switch (get_ucall(vcpu, &uc)) {
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case UCALL_ABORT:
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REPORT_GUEST_ASSERT(uc);
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break;
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case UCALL_PRINTF:
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printf("%s", uc.buffer);
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break;
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case UCALL_DONE:
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break;
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default:
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TEST_FAIL("Unknown ucall %lu", uc.cmd);
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}
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} while (uc.cmd != UCALL_DONE);
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}
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static void test_guest_no_gicv3(void)
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{
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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/* Create a VM without a GICv3 */
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vm = vm_create_with_one_vcpu(&vcpu, guest_code);
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vm_init_descriptor_tables(vm);
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vcpu_init_descriptor_tables(vcpu);
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vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
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ESR_EC_UNKNOWN, guest_undef_handler);
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test_run_vcpu(vcpu);
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kvm_vm_free(vm);
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}
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int main(int argc, char *argv[])
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{
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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uint64_t pfr0;
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vm = vm_create_with_one_vcpu(&vcpu, NULL);
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vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &pfr0);
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__TEST_REQUIRE(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), pfr0),
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"GICv3 not supported.");
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kvm_vm_free(vm);
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test_guest_no_gicv3();
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return 0;
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}

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