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Taniya Dasandersson
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clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Also gpu_cc_cb_clk is recommended to be kept always ON, hence use clk_branch2_aon_ops to keep the clock always ON. Fixes: 0afa16a ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <[email protected]>
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drivers/clk/qcom/gpucc-sa8775p.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = {
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.name = "gpu_cc_ff_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
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.name = "gpu_cc_hub_clk_src",
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.parent_data = gpu_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cb_clk",
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.ops = &clk_branch2_ops,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};

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