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LorenzoBianconivinodkoul
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dt-bindings: phy: airoha: Add PCIe PHY controller
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY controller. Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Lorenzo Bianconi <[email protected]> Link: https://lore.kernel.org/r/656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <[email protected]>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Airoha EN7581 PCI-Express PHY
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maintainers:
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- Lorenzo Bianconi <[email protected]>
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description:
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The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
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properties:
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compatible:
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const: airoha,en7581-pcie-phy
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reg:
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items:
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- description: PCIE analog base address
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- description: PCIE lane0 base address
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- description: PCIE lane1 base address
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reg-names:
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items:
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- const: csr-2l
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- const: pma0
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- const: pma1
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@11e80000 {
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compatible = "airoha,en7581-pcie-phy";
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#phy-cells = <0>;
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reg = <0x0 0x1fa5a000 0x0 0xfff>,
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<0x0 0x1fa5b000 0x0 0xfff>,
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<0x0 0x1fa5c000 0x0 0xfff>;
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reg-names = "csr-2l", "pma0", "pma1";
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};
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};

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