|
371 | 371 | .ops = &axp20x_ops, \
|
372 | 372 | }
|
373 | 373 |
|
374 |
| -#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
375 |
| - _vmask, _ereg, _emask) \ |
| 374 | +#define AXP_DESC_DELAY(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 375 | + _vmask, _ereg, _emask, _ramp_delay) \ |
376 | 376 | [_family##_##_id] = { \
|
377 | 377 | .name = (_match), \
|
378 | 378 | .supply_name = (_supply), \
|
|
388 | 388 | .vsel_mask = (_vmask), \
|
389 | 389 | .enable_reg = (_ereg), \
|
390 | 390 | .enable_mask = (_emask), \
|
| 391 | + .ramp_delay = (_ramp_delay), \ |
391 | 392 | .ops = &axp20x_ops, \
|
392 | 393 | }
|
393 | 394 |
|
| 395 | +#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 396 | + _vmask, _ereg, _emask) \ |
| 397 | + AXP_DESC_DELAY(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 398 | + _vmask, _ereg, _emask, 0) |
| 399 | + |
394 | 400 | #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
|
395 | 401 | [_family##_##_id] = { \
|
396 | 402 | .name = (_match), \
|
|
419 | 425 | .ops = &axp20x_ops_fixed \
|
420 | 426 | }
|
421 | 427 |
|
422 |
| -#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ |
423 |
| - _vreg, _vmask, _ereg, _emask) \ |
| 428 | +#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \ |
| 429 | + _vreg, _vmask, _ereg, _emask, _ramp_delay) \ |
424 | 430 | [_family##_##_id] = { \
|
425 | 431 | .name = (_match), \
|
426 | 432 | .supply_name = (_supply), \
|
|
436 | 442 | .enable_mask = (_emask), \
|
437 | 443 | .linear_ranges = (_ranges), \
|
438 | 444 | .n_linear_ranges = ARRAY_SIZE(_ranges), \
|
| 445 | + .ramp_delay = (_ramp_delay), \ |
439 | 446 | .ops = &axp20x_ops_range, \
|
440 | 447 | }
|
441 | 448 |
|
| 449 | +#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ |
| 450 | + _vreg, _vmask, _ereg, _emask) \ |
| 451 | + AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \ |
| 452 | + _n_voltages, _vreg, _vmask, _ereg, _emask, 0) |
| 453 | + |
442 | 454 | static const int axp209_dcdc2_ldo3_slew_rates[] = {
|
443 | 455 | 1600,
|
444 | 456 | 800,
|
@@ -781,21 +793,21 @@ static const struct linear_range axp717_dcdc3_ranges[] = {
|
781 | 793 | };
|
782 | 794 |
|
783 | 795 | static const struct regulator_desc axp717_regulators[] = {
|
784 |
| - AXP_DESC_RANGES(AXP717, DCDC1, "dcdc1", "vin1", |
| 796 | + AXP_DESC_RANGES_DELAY(AXP717, DCDC1, "dcdc1", "vin1", |
785 | 797 | axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES,
|
786 | 798 | AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK,
|
787 |
| - AXP717_DCDC_OUTPUT_CONTROL, BIT(0)), |
788 |
| - AXP_DESC_RANGES(AXP717, DCDC2, "dcdc2", "vin2", |
| 799 | + AXP717_DCDC_OUTPUT_CONTROL, BIT(0), 640), |
| 800 | + AXP_DESC_RANGES_DELAY(AXP717, DCDC2, "dcdc2", "vin2", |
789 | 801 | axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES,
|
790 | 802 | AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK,
|
791 |
| - AXP717_DCDC_OUTPUT_CONTROL, BIT(1)), |
792 |
| - AXP_DESC_RANGES(AXP717, DCDC3, "dcdc3", "vin3", |
| 803 | + AXP717_DCDC_OUTPUT_CONTROL, BIT(1), 640), |
| 804 | + AXP_DESC_RANGES_DELAY(AXP717, DCDC3, "dcdc3", "vin3", |
793 | 805 | axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES,
|
794 | 806 | AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK,
|
795 |
| - AXP717_DCDC_OUTPUT_CONTROL, BIT(2)), |
796 |
| - AXP_DESC(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100, |
| 807 | + AXP717_DCDC_OUTPUT_CONTROL, BIT(2), 640), |
| 808 | + AXP_DESC_DELAY(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100, |
797 | 809 | AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK,
|
798 |
| - AXP717_DCDC_OUTPUT_CONTROL, BIT(3)), |
| 810 | + AXP717_DCDC_OUTPUT_CONTROL, BIT(3), 6400), |
799 | 811 | AXP_DESC(AXP717, ALDO1, "aldo1", "aldoin", 500, 3500, 100,
|
800 | 812 | AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
|
801 | 813 | AXP717_LDO0_OUTPUT_CONTROL, BIT(0)),
|
|
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