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Merge tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown: "A few fairly small fixes for v6.13, the most substatial one being disabling STIG mode for Cadence QSPI controllers on Altera SoCFPGA platforms since it doesn't work" * tag 'spi-fix-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA. spi: rockchip: Fix PM runtime count on no-op cs spi: aspeed: Fix an error handling path in aspeed_spi_[read|write]_user()
2 parents 4e1b486 + 25fb0e7 commit f861356

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3 files changed

+28
-6
lines changed

3 files changed

+28
-6
lines changed

drivers/spi/spi-aspeed-smc.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
239239

240240
ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
241241
if (ret < 0)
242-
return ret;
242+
goto stop_user;
243243

244244
if (op->dummy.buswidth && op->dummy.nbytes) {
245245
for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
@@ -249,8 +249,9 @@ static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
249249
aspeed_spi_set_io_mode(chip, io_mode);
250250

251251
aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
252+
stop_user:
252253
aspeed_spi_stop_user(chip);
253-
return 0;
254+
return ret;
254255
}
255256

256257
static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
@@ -261,10 +262,11 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
261262
aspeed_spi_start_user(chip);
262263
ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
263264
if (ret < 0)
264-
return ret;
265+
goto stop_user;
265266
aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
267+
stop_user:
266268
aspeed_spi_stop_user(chip);
267-
return 0;
269+
return ret;
268270
}
269271

270272
/* support for 1-1-1, 1-1-2 or 1-1-4 */

drivers/spi/spi-cadence-quadspi.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
4343
#define CQSPI_SLOW_SRAM BIT(4)
4444
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
4545
#define CQSPI_RD_NO_IRQ BIT(6)
46+
#define CQSPI_DISABLE_STIG_MODE BIT(7)
4647

4748
/* Capabilities */
4849
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -103,6 +104,7 @@ struct cqspi_st {
103104
bool apb_ahb_hazard;
104105

105106
bool is_jh7110; /* Flag for StarFive JH7110 SoC */
107+
bool disable_stig_mode;
106108

107109
const struct cqspi_driver_platdata *ddata;
108110
};
@@ -1416,7 +1418,8 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
14161418
* reads, prefer STIG mode for such small reads.
14171419
*/
14181420
if (!op->addr.nbytes ||
1419-
op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
1421+
(op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
1422+
!cqspi->disable_stig_mode))
14201423
return cqspi_command_read(f_pdata, op);
14211424

14221425
return cqspi_read(f_pdata, op);
@@ -1880,6 +1883,8 @@ static int cqspi_probe(struct platform_device *pdev)
18801883
if (ret)
18811884
goto probe_reset_failed;
18821885
}
1886+
if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)
1887+
cqspi->disable_stig_mode = true;
18831888

18841889
if (of_device_is_compatible(pdev->dev.of_node,
18851890
"xlnx,versal-ospi-1.0")) {
@@ -2043,7 +2048,8 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
20432048
static const struct cqspi_driver_platdata socfpga_qspi = {
20442049
.quirks = CQSPI_DISABLE_DAC_MODE
20452050
| CQSPI_NO_SUPPORT_WR_COMPLETION
2046-
| CQSPI_SLOW_SRAM,
2051+
| CQSPI_SLOW_SRAM
2052+
| CQSPI_DISABLE_STIG_MODE,
20472053
};
20482054

20492055
static const struct cqspi_driver_platdata versal_ospi = {

drivers/spi/spi-rockchip.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -241,6 +241,20 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
241241
struct spi_controller *ctlr = spi->controller;
242242
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
243243
bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
244+
bool cs_actual;
245+
246+
/*
247+
* SPI subsystem tries to avoid no-op calls that would break the PM
248+
* refcount below. It can't however for the first time it is used.
249+
* To detect this case we read it here and bail out early for no-ops.
250+
*/
251+
if (spi_get_csgpiod(spi, 0))
252+
cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1);
253+
else
254+
cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) &
255+
BIT(spi_get_chipselect(spi, 0)));
256+
if (unlikely(cs_actual == cs_asserted))
257+
return;
244258

245259
if (cs_asserted) {
246260
/* Keep things powered as long as CS is asserted */

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