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BartoszDunajskiCompute-Runtime-Automation
BartoszDunajski
authored and
Compute-Runtime-Automation
committed
Add ftrTileY flags on Linux
Change-Id: Iec00c137e332ac818ba6958e57c90dccf7629931 Signed-off-by: Dunajski, Bartosz <[email protected]>
1 parent 8615288 commit 2764179

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14 files changed

+226
-211
lines changed

14 files changed

+226
-211
lines changed

‎runtime/gen10/linux/hw_info_config_cnl.inl‎

Lines changed: 32 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2017-2018 Intel Corporation
2+
* Copyright (C) 2017-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -31,45 +31,46 @@ int HwInfoConfigHw<IGFX_CANNONLAKE>::configureHardwareCustom(HardwareInfo *hwInf
3131
pSysInfo->L3CacheSizeInKb -= 256;
3232
}
3333

34-
pSkuTable->ftrGpGpuMidBatchPreempt = 1;
35-
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
36-
pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
37-
pSkuTable->ftr3dMidBatchPreempt = 1;
38-
pSkuTable->ftr3dObjectLevelPreempt = 1;
39-
pSkuTable->ftr3dMidBatchPreempt = 1;
40-
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
41-
pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
34+
pSkuTable->ftrGpGpuMidBatchPreempt = true;
35+
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = true;
36+
pSkuTable->ftrGpGpuMidThreadLevelPreempt = false;
37+
pSkuTable->ftr3dMidBatchPreempt = true;
38+
pSkuTable->ftr3dObjectLevelPreempt = true;
39+
pSkuTable->ftr3dMidBatchPreempt = true;
40+
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = true;
41+
pSkuTable->ftrPerCtxtPreemptionGranularityControl = true;
4242

43-
pSkuTable->ftrPPGTT = 1;
44-
pSkuTable->ftrSVM = 1;
45-
pSkuTable->ftrL3IACoherency = 1;
46-
pSkuTable->ftrIA32eGfxPTEs = 1;
47-
pSkuTable->ftrStandardMipTailFormat = 1;
43+
pSkuTable->ftrPPGTT = true;
44+
pSkuTable->ftrSVM = true;
45+
pSkuTable->ftrL3IACoherency = true;
46+
pSkuTable->ftrIA32eGfxPTEs = true;
47+
pSkuTable->ftrStandardMipTailFormat = true;
4848

49-
pSkuTable->ftrDisplayYTiling = 1;
50-
pSkuTable->ftrTranslationTable = 1;
51-
pSkuTable->ftrUserModeTranslationTable = 1;
52-
pSkuTable->ftrTileMappedResource = 1;
53-
pSkuTable->ftrEnableGuC = 1;
49+
pSkuTable->ftrDisplayYTiling = true;
50+
pSkuTable->ftrTranslationTable = true;
51+
pSkuTable->ftrUserModeTranslationTable = true;
52+
pSkuTable->ftrTileMappedResource = true;
53+
pSkuTable->ftrEnableGuC = true;
5454

55-
pSkuTable->ftrFbc = 1;
56-
pSkuTable->ftrFbc2AddressTranslation = 1;
57-
pSkuTable->ftrFbcBlitterTracking = 1;
58-
pSkuTable->ftrFbcCpuTracking = 1;
55+
pSkuTable->ftrFbc = true;
56+
pSkuTable->ftrFbc2AddressTranslation = true;
57+
pSkuTable->ftrFbcBlitterTracking = true;
58+
pSkuTable->ftrFbcCpuTracking = true;
5959

60-
pSkuTable->ftrAstcHdr2D = 1;
61-
pSkuTable->ftrAstcLdr2D = 1;
60+
pSkuTable->ftrAstcHdr2D = true;
61+
pSkuTable->ftrAstcLdr2D = true;
62+
pSkuTable->ftrTileY = true;
6263

63-
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
64-
pWaTable->waSendMIFLUSHBeforeVFE = 1;
65-
pWaTable->waReportPerfCountUseGlobalContextID = 1;
66-
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
64+
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
65+
pWaTable->waSendMIFLUSHBeforeVFE = true;
66+
pWaTable->waReportPerfCountUseGlobalContextID = true;
67+
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
6768

6869
if ((1 << hwInfo->pPlatform->usRevId) & 0x3) {
69-
pWaTable->waFbcLinearSurfaceStride = 1;
70+
pWaTable->waFbcLinearSurfaceStride = true;
7071
}
7172
if ((1 << hwInfo->pPlatform->usRevId) & 0x1) {
72-
pWaTable->waEncryptedEdramOnlyPartials = 1;
73+
pWaTable->waEncryptedEdramOnlyPartials = true;
7374
}
7475
return 0;
7576
}

‎runtime/gen8/linux/hw_info_config_bdw.inl‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2017-2018 Intel Corporation
2+
* Copyright (C) 2017-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -25,21 +25,22 @@ int HwInfoConfigHw<IGFX_BROADWELL>::configureHardwareCustom(HardwareInfo *hwInfo
2525
pSysInfo->SliceCount = 1;
2626
}
2727

28-
pSkuTable->ftrPPGTT = 1;
29-
pSkuTable->ftrSVM = 1;
30-
pSkuTable->ftrL3IACoherency = 1;
31-
pSkuTable->ftrIA32eGfxPTEs = 1;
32-
33-
pSkuTable->ftrFbc = 1;
34-
pSkuTable->ftrFbc2AddressTranslation = 1;
35-
pSkuTable->ftrFbcBlitterTracking = 1;
36-
pSkuTable->ftrFbcCpuTracking = 1;
37-
38-
pWaTable->waDisableLSQCROPERFforOCL = 1;
39-
pWaTable->waReportPerfCountUseGlobalContextID = 1;
40-
pWaTable->waUseVAlign16OnTileXYBpp816 = 1;
41-
pWaTable->waModifyVFEStateAfterGPGPUPreemption = 1;
42-
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
28+
pSkuTable->ftrPPGTT = true;
29+
pSkuTable->ftrSVM = true;
30+
pSkuTable->ftrL3IACoherency = true;
31+
pSkuTable->ftrIA32eGfxPTEs = true;
32+
33+
pSkuTable->ftrFbc = true;
34+
pSkuTable->ftrFbc2AddressTranslation = true;
35+
pSkuTable->ftrFbcBlitterTracking = true;
36+
pSkuTable->ftrFbcCpuTracking = true;
37+
pSkuTable->ftrTileY = true;
38+
39+
pWaTable->waDisableLSQCROPERFforOCL = true;
40+
pWaTable->waReportPerfCountUseGlobalContextID = true;
41+
pWaTable->waUseVAlign16OnTileXYBpp816 = true;
42+
pWaTable->waModifyVFEStateAfterGPGPUPreemption = true;
43+
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
4344

4445
if (hwInfo->pPlatform->usDeviceID == IBDW_GT3_HALO_MOBL_DEVICE_F0_ID ||
4546
hwInfo->pPlatform->usDeviceID == IBDW_GT3_SERV_DEVICE_F0_ID) {

‎runtime/gen9/linux/hw_info_config_bxt.inl‎

Lines changed: 33 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2017-2018 Intel Corporation
2+
* Copyright (C) 2017-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -24,49 +24,50 @@ int HwInfoConfigHw<IGFX_BROXTON>::configureHardwareCustom(HardwareInfo *hwInfo,
2424

2525
pSysInfo->VEBoxInfo.Instances.Bits.VEBox0Enabled = 1;
2626
pSysInfo->VEBoxInfo.IsValid = true;
27-
pSkuTable->ftrVEBOX = 1;
28-
pSkuTable->ftrULT = 1;
27+
pSkuTable->ftrVEBOX = true;
28+
pSkuTable->ftrULT = true;
2929

30-
pSkuTable->ftrGpGpuMidBatchPreempt = 1;
31-
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
32-
pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
33-
pSkuTable->ftr3dMidBatchPreempt = 1;
34-
pSkuTable->ftr3dObjectLevelPreempt = 1;
35-
pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
30+
pSkuTable->ftrGpGpuMidBatchPreempt = true;
31+
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = true;
32+
pSkuTable->ftrGpGpuMidThreadLevelPreempt = false;
33+
pSkuTable->ftr3dMidBatchPreempt = true;
34+
pSkuTable->ftr3dObjectLevelPreempt = true;
35+
pSkuTable->ftrPerCtxtPreemptionGranularityControl = true;
3636

37-
pSkuTable->ftrLCIA = 1;
38-
pSkuTable->ftrPPGTT = 1;
39-
pSkuTable->ftrL3IACoherency = 1;
40-
pSkuTable->ftrIA32eGfxPTEs = 1;
37+
pSkuTable->ftrLCIA = true;
38+
pSkuTable->ftrPPGTT = true;
39+
pSkuTable->ftrL3IACoherency = true;
40+
pSkuTable->ftrIA32eGfxPTEs = true;
4141

42-
pSkuTable->ftrDisplayYTiling = 1;
43-
pSkuTable->ftrTranslationTable = 1;
44-
pSkuTable->ftrUserModeTranslationTable = 1;
45-
pSkuTable->ftrEnableGuC = 1;
42+
pSkuTable->ftrDisplayYTiling = true;
43+
pSkuTable->ftrTranslationTable = true;
44+
pSkuTable->ftrUserModeTranslationTable = true;
45+
pSkuTable->ftrEnableGuC = true;
4646

47-
pSkuTable->ftrFbc = 1;
48-
pSkuTable->ftrFbc2AddressTranslation = 1;
49-
pSkuTable->ftrFbcBlitterTracking = 1;
50-
pSkuTable->ftrFbcCpuTracking = 1;
47+
pSkuTable->ftrFbc = true;
48+
pSkuTable->ftrFbc2AddressTranslation = true;
49+
pSkuTable->ftrFbcBlitterTracking = true;
50+
pSkuTable->ftrFbcCpuTracking = true;
51+
pSkuTable->ftrTileY = true;
5152

5253
if (pPlatform->usRevId >= 3) {
53-
pSkuTable->ftrGttCacheInvalidation = 1;
54+
pSkuTable->ftrGttCacheInvalidation = true;
5455
}
5556

56-
pWaTable->waLLCCachingUnsupported = 1;
57-
pWaTable->waMsaa8xTileYDepthPitchAlignment = 1;
58-
pWaTable->waFbcLinearSurfaceStride = 1;
59-
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
60-
pWaTable->waEnablePreemptionGranularityControlByUMD = 1;
61-
pWaTable->waSendMIFLUSHBeforeVFE = 1;
62-
pWaTable->waForcePcBbFullCfgRestore = 1;
63-
pWaTable->waReportPerfCountUseGlobalContextID = 1;
64-
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
57+
pWaTable->waLLCCachingUnsupported = true;
58+
pWaTable->waMsaa8xTileYDepthPitchAlignment = true;
59+
pWaTable->waFbcLinearSurfaceStride = true;
60+
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
61+
pWaTable->waEnablePreemptionGranularityControlByUMD = true;
62+
pWaTable->waSendMIFLUSHBeforeVFE = true;
63+
pWaTable->waForcePcBbFullCfgRestore = true;
64+
pWaTable->waReportPerfCountUseGlobalContextID = true;
65+
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
6566

6667
int enabled = 0;
6768
int retVal = drm->getEnabledPooledEu(enabled);
6869
if (retVal == 0) {
69-
pSkuTable->ftrPooledEuEnabled = (enabled != 0) ? 1 : 0;
70+
pSkuTable->ftrPooledEuEnabled = (enabled != 0);
7071
}
7172
if (enabled) {
7273
int num = 0;

‎runtime/gen9/linux/hw_info_config_cfl.inl‎

Lines changed: 30 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2018 Intel Corporation
2+
* Copyright (C) 2018-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -22,40 +22,41 @@ int HwInfoConfigHw<IGFX_COFFEELAKE>::configureHardwareCustom(HardwareInfo *hwInf
2222
pSysInfo->SliceCount = 1;
2323
}
2424

25-
pSysInfo->VEBoxInfo.Instances.Bits.VEBox0Enabled = 1;
25+
pSysInfo->VEBoxInfo.Instances.Bits.VEBox0Enabled = true;
2626
pSysInfo->VEBoxInfo.IsValid = true;
27-
pSkuTable->ftrVEBOX = 1;
27+
pSkuTable->ftrVEBOX = true;
2828

29-
pSkuTable->ftrGpGpuMidBatchPreempt = 1;
30-
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
31-
pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
32-
pSkuTable->ftr3dMidBatchPreempt = 1;
33-
pSkuTable->ftr3dObjectLevelPreempt = 1;
34-
pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
29+
pSkuTable->ftrGpGpuMidBatchPreempt = true;
30+
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = true;
31+
pSkuTable->ftrGpGpuMidThreadLevelPreempt = false;
32+
pSkuTable->ftr3dMidBatchPreempt = true;
33+
pSkuTable->ftr3dObjectLevelPreempt = true;
34+
pSkuTable->ftrPerCtxtPreemptionGranularityControl = true;
3535

36-
pSkuTable->ftrPPGTT = 1;
37-
pSkuTable->ftrSVM = 1;
38-
pSkuTable->ftrL3IACoherency = 1;
39-
pSkuTable->ftrIA32eGfxPTEs = 1;
36+
pSkuTable->ftrPPGTT = true;
37+
pSkuTable->ftrSVM = true;
38+
pSkuTable->ftrL3IACoherency = true;
39+
pSkuTable->ftrIA32eGfxPTEs = true;
4040

41-
pSkuTable->ftrDisplayYTiling = 1;
42-
pSkuTable->ftrTranslationTable = 1;
43-
pSkuTable->ftrUserModeTranslationTable = 1;
44-
pSkuTable->ftrEnableGuC = 1;
41+
pSkuTable->ftrDisplayYTiling = true;
42+
pSkuTable->ftrTranslationTable = true;
43+
pSkuTable->ftrUserModeTranslationTable = true;
44+
pSkuTable->ftrEnableGuC = true;
4545

46-
pSkuTable->ftrFbc = 1;
47-
pSkuTable->ftrFbc2AddressTranslation = 1;
48-
pSkuTable->ftrFbcBlitterTracking = 1;
49-
pSkuTable->ftrFbcCpuTracking = 1;
46+
pSkuTable->ftrFbc = true;
47+
pSkuTable->ftrFbc2AddressTranslation = true;
48+
pSkuTable->ftrFbcBlitterTracking = true;
49+
pSkuTable->ftrFbcCpuTracking = true;
50+
pSkuTable->ftrTileY = true;
5051

51-
pWaTable->waEnablePreemptionGranularityControlByUMD = 1;
52-
pWaTable->waSendMIFLUSHBeforeVFE = 1;
53-
pWaTable->waReportPerfCountUseGlobalContextID = 1;
54-
pWaTable->waMsaa8xTileYDepthPitchAlignment = 1;
55-
pWaTable->waLosslessCompressionSurfaceStride = 1;
56-
pWaTable->waFbcLinearSurfaceStride = 1;
57-
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
58-
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
52+
pWaTable->waEnablePreemptionGranularityControlByUMD = true;
53+
pWaTable->waSendMIFLUSHBeforeVFE = true;
54+
pWaTable->waReportPerfCountUseGlobalContextID = true;
55+
pWaTable->waMsaa8xTileYDepthPitchAlignment = true;
56+
pWaTable->waLosslessCompressionSurfaceStride = true;
57+
pWaTable->waFbcLinearSurfaceStride = true;
58+
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
59+
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
5960

6061
if (hwInfo->pPlatform->usDeviceID == ICFL_GT3_ULT_28W_DEVICE_F0_ID ||
6162
hwInfo->pPlatform->usDeviceID == ICFL_GT3_ULT_15W_DEVICE_F0_ID) {

‎runtime/gen9/linux/hw_info_config_glk.inl‎

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2017-2018 Intel Corporation
2+
* Copyright (C) 2017-2019 Intel Corporation
33
*
44
* SPDX-License-Identifier: MIT
55
*
@@ -22,40 +22,41 @@ int HwInfoConfigHw<IGFX_GEMINILAKE>::configureHardwareCustom(HardwareInfo *hwInf
2222
pSysInfo->VEBoxInfo.Instances.Bits.VEBox0Enabled = 1;
2323
pSysInfo->VEBoxInfo.IsValid = true;
2424

25-
pSkuTable->ftrGpGpuMidBatchPreempt = 1;
26-
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
27-
pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
28-
pSkuTable->ftr3dMidBatchPreempt = 1;
29-
pSkuTable->ftr3dObjectLevelPreempt = 1;
30-
pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
25+
pSkuTable->ftrGpGpuMidBatchPreempt = true;
26+
pSkuTable->ftrGpGpuThreadGroupLevelPreempt = true;
27+
pSkuTable->ftrGpGpuMidThreadLevelPreempt = false;
28+
pSkuTable->ftr3dMidBatchPreempt = true;
29+
pSkuTable->ftr3dObjectLevelPreempt = true;
30+
pSkuTable->ftrPerCtxtPreemptionGranularityControl = true;
3131

32-
pSkuTable->ftrLCIA = 1;
33-
pSkuTable->ftrPPGTT = 1;
34-
pSkuTable->ftrL3IACoherency = 1;
35-
pSkuTable->ftrIA32eGfxPTEs = 1;
32+
pSkuTable->ftrLCIA = true;
33+
pSkuTable->ftrPPGTT = true;
34+
pSkuTable->ftrL3IACoherency = true;
35+
pSkuTable->ftrIA32eGfxPTEs = true;
3636

37-
pSkuTable->ftrTranslationTable = 1;
38-
pSkuTable->ftrUserModeTranslationTable = 1;
39-
pSkuTable->ftrEnableGuC = 1;
40-
pSkuTable->ftrTileMappedResource = 1;
41-
pSkuTable->ftrULT = 1;
42-
pSkuTable->ftrAstcHdr2D = 1;
43-
pSkuTable->ftrAstcLdr2D = 1;
37+
pSkuTable->ftrTranslationTable = true;
38+
pSkuTable->ftrUserModeTranslationTable = true;
39+
pSkuTable->ftrEnableGuC = true;
40+
pSkuTable->ftrTileMappedResource = true;
41+
pSkuTable->ftrULT = true;
42+
pSkuTable->ftrAstcHdr2D = true;
43+
pSkuTable->ftrAstcLdr2D = true;
44+
pSkuTable->ftrTileY = true;
4445

45-
pWaTable->waLLCCachingUnsupported = 1;
46-
pWaTable->waMsaa8xTileYDepthPitchAlignment = 1;
47-
pWaTable->waFbcLinearSurfaceStride = 1;
48-
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
49-
pWaTable->waEnablePreemptionGranularityControlByUMD = 1;
50-
pWaTable->waSendMIFLUSHBeforeVFE = 1;
51-
pWaTable->waForcePcBbFullCfgRestore = 1;
52-
pWaTable->waReportPerfCountUseGlobalContextID = 1;
53-
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
46+
pWaTable->waLLCCachingUnsupported = true;
47+
pWaTable->waMsaa8xTileYDepthPitchAlignment = true;
48+
pWaTable->waFbcLinearSurfaceStride = true;
49+
pWaTable->wa4kAlignUVOffsetNV12LinearSurface = true;
50+
pWaTable->waEnablePreemptionGranularityControlByUMD = true;
51+
pWaTable->waSendMIFLUSHBeforeVFE = true;
52+
pWaTable->waForcePcBbFullCfgRestore = true;
53+
pWaTable->waReportPerfCountUseGlobalContextID = true;
54+
pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
5455

5556
int enabled = 0;
5657
int retVal = drm->getEnabledPooledEu(enabled);
5758
if (retVal == 0) {
58-
pSkuTable->ftrPooledEuEnabled = (enabled != 0) ? 1 : 0;
59+
pSkuTable->ftrPooledEuEnabled = (enabled != 0);
5960
}
6061
if (enabled) {
6162
int num = 0;

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