Refactor internal interface

Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <[email protected]>

Author: zzdanowicz

level_zero/core/source/cmdlist/cmdlist_hw_base.inl

@@ -79,7 +79,7 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendLaunchKernelWithParams(z
 
     KernelImp *kernelImp = static_cast<KernelImp *>(kernel);
     this->containsStatelessUncachedResource |= kernelImp->getKernelRequiresUncachedMocs();
-
+    uint32_t partitionCount = 0;
     NEO::EncodeDispatchKernel<GfxFamily>::encode(commandContainer,
                                                  reinterpret_cast<const void *>(pThreadGroupDimensions),
                                                  isIndirect,
@@ -88,7 +88,8 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendLaunchKernelWithParams(z
                                                  0,
                                                  device->getNEODevice(),
                                                  commandListPreemptionMode,
-                                                 this->containsStatelessUncachedResource);
+                                                 this->containsStatelessUncachedResource,
+                                                 partitionCount);
 
     if (device->getNEODevice()->getDebugger()) {
         auto *ssh = commandContainer.getIndirectHeap(NEO::HeapType::SURFACE_STATE);

shared/source/command_container/command_encoder.h

@@ -37,7 +37,8 @@ struct EncodeDispatchKernel {
                        uint64_t eventAddress,
                        Device *device,
                        PreemptionMode preemptionMode,
-                       bool &requiresUncachedMocs);
+                       bool &requiresUncachedMocs,
+                       uint32_t &partitionCount);
 
     static void encodeAdditionalWalkerFields(const HardwareInfo &hwInfo, WALKER_TYPE &walkerCmd);
 

shared/source/command_container/command_encoder_bdw_plus.inl

@@ -25,7 +25,8 @@ namespace NEO {
 template <typename Family>
 void EncodeDispatchKernel<Family>::encode(CommandContainer &container,
                                           const void *pThreadGroupDimensions, bool isIndirect, bool isPredicate, DispatchKernelEncoderI *dispatchInterface,
-                                          uint64_t eventAddress, Device *device, PreemptionMode preemptionMode, bool &requiresUncachedMocs) {
+                                          uint64_t eventAddress, Device *device, PreemptionMode preemptionMode, bool &requiresUncachedMocs,
+                                          uint32_t &partitionCount) {
 
     using MEDIA_STATE_FLUSH = typename Family::MEDIA_STATE_FLUSH;
     using MEDIA_INTERFACE_DESCRIPTOR_LOAD = typename Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD;
@@ -215,6 +216,8 @@ void EncodeDispatchKernel<Family>::encode(CommandContainer &container,
         auto mediaStateFlush = listCmdBufferStream->getSpace(sizeof(MEDIA_STATE_FLUSH));
         *reinterpret_cast<MEDIA_STATE_FLUSH *>(mediaStateFlush) = Family::cmdInitMediaStateFlush;
     }
+
+    partitionCount = 1;
 }
 
 template <typename Family>

shared/source/generated/gen11/hw_cmds_generated_gen11.inl

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2020 Intel Corporation
+ * Copyright (C) 2018-2021 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -867,6 +867,7 @@ typedef struct tagMI_ATOMIC {
         MEMORYADDRESS_INDEX = 0x1,
     } PATCH_CONSTANTS;
     typedef enum tagATOMIC_OPCODES {
+        ATOMIC_4B_MOVE = 0x4,
         ATOMIC_4B_INCREMENT = 0x5,
         ATOMIC_4B_DECREMENT = 0x6,
         ATOMIC_8B_INCREMENT = 0x25,

shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2020 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -904,6 +904,7 @@ typedef struct tagMI_ATOMIC {
         COMMAND_TYPE_MI_COMMAND = 0x0,
     } COMMAND_TYPE;
     typedef enum tagATOMIC_OPCODES {
+        ATOMIC_4B_MOVE = 0x4,
         ATOMIC_4B_INCREMENT = 0x5,
         ATOMIC_4B_DECREMENT = 0x6,
         ATOMIC_8B_INCREMENT = 0x25,

shared/source/generated/gen8/hw_cmds_generated_gen8.inl

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2020 Intel Corporation
+ * Copyright (C) 2017-2021 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -1005,6 +1005,7 @@ typedef struct tagMI_ATOMIC {
         MEMORYADDRESS_INDEX = 0x1,
     } PATCH_CONSTANTS;
     typedef enum tagATOMIC_OPCODES {
+        ATOMIC_4B_MOVE = 0x4,
         ATOMIC_4B_INCREMENT = 0x5,
         ATOMIC_4B_DECREMENT = 0x6,
         ATOMIC_8B_INCREMENT = 0x25,

shared/source/generated/gen9/hw_cmds_generated_gen9.inl

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2020 Intel Corporation
+ * Copyright (C) 2017-2021 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -1002,6 +1002,7 @@ typedef struct tagMI_ATOMIC {
         MEMORYADDRESS_INDEX = 0x1,
     } PATCH_CONSTANTS;
     typedef enum tagATOMIC_OPCODES {
+        ATOMIC_4B_MOVE = 0x4,
         ATOMIC_4B_INCREMENT = 0x5,
         ATOMIC_4B_DECREMENT = 0x6,
         ATOMIC_8B_INCREMENT = 0x25,