Fix GPU debugging on gen11+

Format of debug mode register changed for gen11+ projects. Without this
change, the SIP is never invoked.

Change-Id: Ie8314acbee1ead527deeea45cb5689b4a39df24c

Author: barreyra

core/helpers/preamble.h

@@ -81,8 +81,10 @@ struct L3CNTLRegisterOffset {
 };
 
 namespace DebugModeRegisterOffset {
-static constexpr uint32_t registerOffset = 0x20ec;
-static constexpr uint32_t debugEnabledValue = (1 << 6) | (1 << 22);
+template <typename GfxFamily>
+constexpr uint32_t registerOffset = 0x20ec;
+template <typename GfxFamily>
+constexpr uint32_t debugEnabledValue = (1 << 6) | (1 << 22);
 }; // namespace DebugModeRegisterOffset
 
 namespace TdDebugControlRegisterOffset {

core/helpers/preamble_base.inl

@@ -89,8 +89,8 @@ template <typename GfxFamily>
 void PreambleHelper<GfxFamily>::programKernelDebugging(LinearStream *pCommandStream) {
     auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
     *pCmd = GfxFamily::cmdInitLoadRegisterImm;
-    pCmd->setRegisterOffset(DebugModeRegisterOffset::registerOffset);
-    pCmd->setDataDword(DebugModeRegisterOffset::debugEnabledValue);
+    pCmd->setRegisterOffset(DebugModeRegisterOffset::registerOffset<GfxFamily>);
+    pCmd->setDataDword(DebugModeRegisterOffset::debugEnabledValue<GfxFamily>);
 
     auto pCmd2 = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
     *pCmd2 = GfxFamily::cmdInitLoadRegisterImm;

core/unit_tests/preamble/preamble_tests.cpp

@@ -9,6 +9,7 @@
 #include "core/unit_tests/helpers/debug_manager_state_restore.h"
 #include "core/utilities/stackvec.h"
 #include "runtime/command_stream/preemption.h"
+#include "runtime/gen11/reg_configs.h"
 #include "runtime/helpers/flat_batch_buffer_helper_hw.h"
 #include "test.h"
 #include "unit_tests/helpers/hw_parse.h"
@@ -120,9 +121,8 @@ HWTEST_F(PreambleTest, whenKernelDebuggingCommandsAreProgrammedThenCorrectComman
     auto it = cmdList.begin();
 
     MI_LOAD_REGISTER_IMM *pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*it);
-    EXPECT_EQ(DebugModeRegisterOffset::registerOffset, pCmd->getRegisterOffset());
-    EXPECT_EQ(DebugModeRegisterOffset::debugEnabledValue, pCmd->getDataDword());
-
+    EXPECT_EQ(DebugModeRegisterOffset::registerOffset<FamilyType>, pCmd->getRegisterOffset());
+    EXPECT_EQ(DebugModeRegisterOffset::debugEnabledValue<FamilyType>, pCmd->getDataDword());
     it++;
 
     pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*it);

runtime/gen11/reg_configs.h

@@ -23,6 +23,13 @@ struct L3CNTLRegisterOffset<ICLFamily> {
     static const uint32_t registerOffset = 0x7034;
 };
 
+namespace DebugModeRegisterOffset {
+template <>
+constexpr uint32_t registerOffset<ICLFamily> = 0x20d8;
+template <>
+constexpr uint32_t debugEnabledValue<ICLFamily> = (1 << 5) | (1 << 21);
+}; // namespace DebugModeRegisterOffset
+
 namespace gen11HdcModeRegister {
 const uint32_t address = 0xE5F4;
 const uint32_t forceNonCoherentEnableBit = 4;