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[efiwrapper][xDCI] support bar above 4GB
When run as Acrn guest, xDCI/xHCI bar may above 4GB. This patch support bar above 4GB. Change-Id: Id1e47b6cd79ba5698b3086391bba19c41a29c0e8 Tracked-On: https://jira.devtools.intel.com/browse/OAM-77701 Signed-off-by: JianFeng,Zhou <[email protected]> Reviewed-on: https://android.intel.com:443/664210
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+51
-34
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4 files changed

+51
-34
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‎drivers/dw3/XdciDWC.c‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424

2525
UINT32
2626
usb_reg_read (
27-
IN UINT32 base,
27+
IN UINTN base,
2828
IN UINT32 offset
2929
)
3030
{
@@ -34,7 +34,7 @@ usb_reg_read (
3434

3535
VOID
3636
usb_reg_write (
37-
IN UINT32 base,
37+
IN UINTN base,
3838
IN UINT32 offset,
3939
IN UINT32 val
4040
)
@@ -250,7 +250,7 @@ dwc_xdci_core_issue_ep_cmd (
250250
IN DWC_XDCI_ENDPOINT_CMD_PARAMS *ep_cmd_params
251251
)
252252
{
253-
UINT32 base_addr;
253+
UINTN base_addr;
254254
UINT32 max_delay_iter = 5000;//DWC_XDCI_MAX_DELAY_ITERATIONS;
255255

256256
if (core_handle == NULL) {
@@ -315,7 +315,7 @@ dwc_xdci_core_flush_all_fifos (
315315
IN XDCI_CORE_HANDLE *core_handle
316316
)
317317
{
318-
UINT32 base_addr;
318+
UINTN base_addr;
319319
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
320320

321321
if (core_handle == NULL) {
@@ -363,7 +363,7 @@ dwc_xdci_core_flush_ep_tx_fifo (
363363
__attribute__((__unused__)) IN UINT32 ep_num
364364
)
365365
{
366-
UINT32 base_addr;
366+
UINTN base_addr;
367367
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
368368
//UINT32 fifo_num;
369369

@@ -742,7 +742,7 @@ dwc_xdci_process_device_reset_done (
742742
)
743743
{
744744
DWC_XDCI_ENDPOINT_CMD_PARAMS ep_cmd_params;
745-
UINT32 base_addr;
745+
UINTN base_addr;
746746
EFI_STATUS status = EFI_SUCCESS;
747747

748748
if (core_handle == NULL) {
@@ -1356,7 +1356,7 @@ dwc_xdci_core_init (
13561356
)
13571357
{
13581358
EFI_STATUS status = EFI_DEVICE_ERROR;
1359-
UINT32 base_addr;
1359+
UINTN base_addr;
13601360
XDCI_CORE_HANDLE *local_core_handle;
13611361
DWC_XDCI_ENDPOINT_CMD_PARAMS ep_cmd_params;
13621362
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
@@ -1996,7 +1996,7 @@ dwc_xdci_core_isr_routine (
19961996
)
19971997
{
19981998
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
1999-
UINT32 base_addr;
1999+
UINTN base_addr;
20002000
UINT32 event_count;
20012001
UINT32 processed_event_count;
20022002
UINT32 i;
@@ -2055,7 +2055,7 @@ dwc_xdci_core_isr_routine_timer_based (
20552055
)
20562056
{
20572057
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
2058-
UINT32 base_addr;
2058+
UINTN base_addr;
20592059
UINT32 event_count;
20602060
UINT32 processed_event_count;
20612061
UINT32 current_event_addr;
@@ -2131,7 +2131,7 @@ dwc_xdci_core_connect (
21312131
{
21322132
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
21332133
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
2134-
UINT32 base_addr;
2134+
UINTN base_addr;
21352135

21362136
if (core_handle == NULL) {
21372137
DEBUG ((DEBUG_INFO, "dwc_xdci_core_connect: INVALID handle\n"));
@@ -2188,7 +2188,7 @@ dwc_xdci_core_disconnect (
21882188
{
21892189
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
21902190
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
2191-
UINT32 base_addr;
2191+
UINTN base_addr;
21922192
UINT32 event_count;
21932193
UINT32 dsts;
21942194
UINT32 i;
@@ -2291,7 +2291,7 @@ dwc_xdci_core_set_address (
22912291
)
22922292
{
22932293
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
2294-
UINT32 base_addr;
2294+
UINTN base_addr;
22952295

22962296
if (core_handle == NULL) {
22972297
DEBUG ((DEBUG_INFO, "dwc_xdci_core_set_address: INVALID handle\n"));
@@ -2399,7 +2399,7 @@ dwc_xdci_set_link_state (
23992399
)
24002400
{
24012401
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
2402-
UINT32 base_addr;
2402+
UINTN base_addr;
24032403

24042404
if (core_handle == NULL) {
24052405
DEBUG ((DEBUG_INFO, "dwc_xdci_set_link_state: INVALID handle\n"));
@@ -2534,7 +2534,7 @@ dwc_xdci_ep_enable (
25342534
{
25352535
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
25362536
UINT32 ep_num;
2537-
UINT32 base_addr;
2537+
UINTN base_addr;
25382538

25392539
if (core_handle == NULL) {
25402540
DEBUG ((DEBUG_INFO, "dwc_xdci_ep_enable: INVALID handle\n"));
@@ -2574,7 +2574,7 @@ dwc_xdci_ep_disable (
25742574
{
25752575
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
25762576
UINT32 ep_num;
2577-
UINT32 base_addr;
2577+
UINTN base_addr;
25782578

25792579
if (core_handle == NULL) {
25802580
DEBUG ((DEBUG_INFO, "dwc_xdci_ep_disable: INVALID handle\n"));
@@ -2718,7 +2718,7 @@ dwc_xdci_ep_set_nrdy (
27182718
{
27192719
XDCI_CORE_HANDLE *local_core_handle = (XDCI_CORE_HANDLE *)core_handle;
27202720
UINT32 ep_num;
2721-
UINT32 base_addr;
2721+
UINTN base_addr;
27222722
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
27232723

27242724
if (core_handle == NULL) {
@@ -2853,7 +2853,7 @@ dwc_xdci_ep0_receive_status_pkt (
28532853
DWC_XDCI_TRB_CONTROL trb_ctrl;
28542854
DWC_XDCI_ENDPOINT_CMD_PARAMS ep_cmd_params;
28552855
EFI_STATUS Status;
2856-
UINT32 base_addr;
2856+
UINTN base_addr;
28572857

28582858
if (core_handle == NULL) {
28592859
DEBUG ((DEBUG_INFO, "dwc_xdci_ep0_receive_status_pkt: INVALID handle\n"));
@@ -2937,7 +2937,7 @@ dwc_xdci_ep0_send_status_pkt (
29372937
DWC_XDCI_TRB *trb;
29382938
DWC_XDCI_ENDPOINT_CMD_PARAMS ep_cmd_params;
29392939
EFI_STATUS Status;
2940-
UINT32 base_addr;
2940+
UINTN base_addr;
29412941

29422942
if (core_handle == NULL) {
29432943
DEBUG ((DEBUG_INFO, "dwc_xdci_ep0_send_status_pkt: INVALID handle\n"));
@@ -3013,7 +3013,7 @@ dwc_xdci_ep_tx_data (
30133013
DWC_XDCI_TRB_CONTROL trb_ctrl;
30143014
EFI_STATUS Status;
30153015
UINT32 ep_num;
3016-
UINT32 base_addr;
3016+
UINTN base_addr;
30173017

30183018
if (core_handle == NULL) {
30193019
DEBUG ((DEBUG_INFO, "dwc_xdci_ep_tx_data: INVALID handle\n"));
@@ -3118,7 +3118,7 @@ dwc_xdci_ep_rx_data (
31183118
DWC_XDCI_TRB_CONTROL trb_ctrl;
31193119
EFI_STATUS Status;
31203120
UINT32 ep_num;
3121-
UINT32 base_addr;
3121+
UINTN base_addr;
31223122

31233123
if (core_handle == NULL) {
31243124
DEBUG ((DEBUG_INFO, "dwc_xdci_ep_rx_data: INVALID handle\n"));
@@ -3209,7 +3209,7 @@ dwc_xdci_core_flush_ep_fifo (
32093209
IN UINT32 ep_num
32103210
)
32113211
{
3212-
UINT32 base_addr;
3212+
UINTN base_addr;
32133213
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;
32143214
UINT32 fifo_num;
32153215
UINT32 Param;
@@ -3342,7 +3342,7 @@ usb_xdci_core_reinit (
33423342
)
33433343
{
33443344
EFI_STATUS status = EFI_DEVICE_ERROR;
3345-
UINT32 base_addr;
3345+
UINTN base_addr;
33463346
XDCI_CORE_HANDLE *local_core_handle;
33473347
DWC_XDCI_ENDPOINT_CMD_PARAMS ep_cmd_params;
33483348
UINT32 max_delay_iter = DWC_XDCI_MAX_DELAY_ITERATIONS;

‎drivers/dw3/XdciDWC.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ typedef struct {
474474
USB_ROLE role; // Desired role i.e. host, device or OTG
475475
USB_SPEED actual_speed; // Actual speed
476476
USB_DEVICE_STATE dev_state; // Device state
477-
UINT32 base_address; // Register base address
477+
UINTN base_address; // Register base address
478478
UINT32 flags; // Init flags
479479
UINT32 max_dev_int_lines; // One event buffer per interrupt line
480480
DWC_XDCI_EVENT_BUFFER event_buffers [DWC_XDCI_MAX_EVENTS_PER_BUFFER * 2]; // Event buffer pool
@@ -676,13 +676,13 @@ usb_get_physical_ep_num (
676676

677677
UINT32
678678
usb_reg_read (
679-
IN UINT32 base,
679+
IN UINTN base,
680680
IN UINT32 offset
681681
);
682682

683683
VOID
684684
usb_reg_write (
685-
IN UINT32 base,
685+
IN UINTN base,
686686
IN UINT32 offset,
687687
IN UINT32 val
688688
);

‎drivers/dw3/XdciDevice.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
*/
2020
typedef struct {
2121
USB_CONTROLLER_ID ControllerId; // Controller ID of the core
22-
UINT32 BaseAddress; // Base address of the controller registers and on-chip memory
22+
UINTN BaseAddress; // Base address of the controller registers and on-chip memory
2323
UINT32 Flags; // Initialization flags
2424
USB_SPEED Speed; // Desired USB bus speed
2525
USB_ROLE Role; // Default USB role

‎drivers/dw3/dw3.c‎

Lines changed: 25 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -786,11 +786,30 @@ UsbdEpRxData (
786786
return Status;
787787
}
788788

789+
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
790+
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
791+
static uint64_t pci_read_bar64(pcidev_t device)
792+
{
793+
uint64_t addr64;
794+
uint32_t addr;
795+
796+
addr = pci_read_config32(device, PCI_BASE_ADDRESS_0);
797+
if ((addr & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != PCI_BASE_ADDRESS_MEM_TYPE_64)
798+
return addr & ~0xf;
799+
800+
addr64 = pci_read_config32(device, PCI_BASE_ADDRESS_0 + 4);
801+
addr64 <<= 32;
802+
addr64 |= addr & ~0xf;
803+
804+
return addr64;
805+
}
806+
789807
static EFIAPI EFI_STATUS
790808
_usb_init_xdci(EFI_USB_DEVICE_MODE_PROTOCOL *This)
791809
{
792810
EFI_STATUS status;
793-
uint32_t addr, pci_command;
811+
uint32_t pci_command;
812+
UINTN addr_hci;
794813
pcidev_t pci_dev;
795814

796815
#if defined(FB_SET_USB_DEVICE_MODE)
@@ -811,10 +830,8 @@ _usb_init_xdci(EFI_USB_DEVICE_MODE_PROTOCOL *This)
811830
ewdbg("PCI xDCI [%x:%x] %d.%d.%d", INTEL_VID, XDCI_PID,
812831
PCI_BUS(pci_dev), PCI_SLOT(pci_dev), PCI_FUNC(pci_dev));
813832

814-
addr = pci_read_config32(pci_dev, PCI_BASE_ADDRESS_0);
815-
addr = addr & ~0xf;
816-
817-
config_params.BaseAddress = addr;
833+
config_params.BaseAddress = (UINTN)pci_read_bar64(pci_dev);
834+
ewdbg("xDCI BaseAddress =0x%llx\n", (uint64_t)config_params.BaseAddress);
818835

819836
/* configure xDCI as a system bus master */
820837
pci_command = pci_read_config32(pci_dev, PCI_COMMAND);
@@ -827,16 +844,16 @@ _usb_init_xdci(EFI_USB_DEVICE_MODE_PROTOCOL *This)
827844
ewdbg("PCI xHCI [%x:%x] %d.%d.%d", INTEL_VID, XHCI_PID,
828845
PCI_BUS(pci_dev), PCI_SLOT(pci_dev), PCI_FUNC(pci_dev));
829846

830-
addr = pci_read_config32(pci_dev, PCI_BASE_ADDRESS_0);
831-
addr = addr & ~0xf;
847+
addr_hci = (UINTN)pci_read_bar64(pci_dev);
848+
ewdbg("xHCI BaseAddress =0x%llx\n", (uint64_t)addr_hci);
832849

833850
/* enable xHCI bus master and I/O access */
834851
pci_command = pci_read_config32(pci_dev, PCI_COMMAND);
835852
pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
836853
pci_write_config32(pci_dev, PCI_COMMAND, pci_command);
837854

838855
/* configure device role */
839-
usb_reg_write(addr, R_XHCI_MEM_DUAL_ROLE_CFG0, CFG0_DEVICE_ROLE_CONFIG);
856+
usb_reg_write(addr_hci, R_XHCI_MEM_DUAL_ROLE_CFG0, CFG0_DEVICE_ROLE_CONFIG);
840857

841858
/* disable xHCI bus master and I/O access */
842859
pci_command &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

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