Skip to content

Actions: intel/intel-graphics-compiler

Actions

Build IGC

Actions

Loading...
Loading

Show workflow options

Create status badge

Loading
build-IGC.yml
928 workflow run results
928 workflow run results

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

Support more scenarios in ShrinkArrayAlloca Build IGC #6832: Commit 332d61e pushed by VPG-SWE-Github
29m 33s master
master
29m 33s
Backport of "[IR] Unify max alignment for arguments with generic max… Build IGC #6831: Commit 77c938c pushed by VPG-SWE-Github
30m 4s master
master
30m 4s
Fix bug for gather send optimization Build IGC #6830: Commit 84b432b pushed by VPG-SWE-Github
30m 7s master
master
30m 7s
[Autobackout][FunctionalRegression]Revert of change: e653864f8ae08ebd… Build IGC #6829: Commit d166721 pushed by VPG-SWE-Github
30m 19s master
master
30m 19s
Emit a bitcast after select in SimplifyConstant Build IGC #6828: Commit ed8790f pushed by VPG-SWE-Github
29m 44s master
master
29m 44s
Get argument type from ByVal instead of pointer type. Build IGC #6827: Commit f625438 pushed by VPG-SWE-Github
30m 32s master
master
30m 32s
Fixed memory leak Build IGC #6826: Commit 9f7cef6 pushed by VPG-SWE-Github
30m 9s master
master
30m 9s
[Autobackout][FunctionalRegression]Revert of change: f6c0fb7e76a8b670… Build IGC #6825: Commit 57460e8 pushed by VPG-SWE-Github
30m 23s master
master
30m 23s
Add ActiveThreadsOnlyBarrier option for OpenCL shaders Build IGC #6824: Commit 80d7ca2 pushed by VPG-SWE-Github
30m 36s master
master
30m 36s
Refactor SIMDInfo Build IGC #6823: Commit e653864 pushed by VPG-SWE-Github
34m 57s master
master
34m 57s
Enable round robin RA for address register Build IGC #6822: Commit 21fcf90 pushed by VPG-SWE-Github
30m 24s master
master
30m 24s
Change polarity of RayQueryDynamicRayManagment opt flag/ail Build IGC #6821: Commit 4b5b508 pushed by VPG-SWE-Github
29m 23s master
master
29m 23s
Changes in code. Build IGC #6820: Commit b92ce53 pushed by VPG-SWE-Github
30m 17s master
master
30m 17s
Enable round robin RA for address register Build IGC #6819: Commit febd1af pushed by VPG-SWE-Github
30m 6s master
master
30m 6s
Remove ISA_RESERVED_9D opcode from vISA Build IGC #6818: Commit e50537c pushed by VPG-SWE-Github
30m 17s master
master
30m 17s
Check number of calls per kernel for inlining Build IGC #6817: Commit 4a7f81a pushed by VPG-SWE-Github
30m 8s master
master
30m 8s
[LLVM15] Switch to LLVM 15 Build IGC #6816: Commit 374a909 pushed by VPG-SWE-Github
30m 20s master
master
30m 20s
Minor refactor Build IGC #6815: Commit 8758ab6 pushed by VPG-SWE-Github
30m 26s master
master
30m 26s
rename ShortImplicitPayloadHeader to GlobalOffset Build IGC #6814: Commit 198c08e pushed by VPG-SWE-Github
30m 14s master
master
30m 14s
Fix crashes encountered during the compilation of Blender kernels ut… Build IGC #6813: Commit c5c2623 pushed by VPG-SWE-Github
30m 8s master
master
30m 8s
gather send optimization Build IGC #6812: Commit b13a1f8 pushed by VPG-SWE-Github
30m 10s master
master
30m 10s
Changes in code. Build IGC #6811: Commit e37fe2e pushed by VPG-SWE-Github
30m 12s master
master
30m 12s
Add tests using regkey OverrideHWGenerateLID Build IGC #6810: Commit 110047b pushed by VPG-SWE-Github
29m 31s master
master
29m 31s
disable ShortImplicitPayloadHeader Build IGC #6809: Commit ce68f84 pushed by VPG-SWE-Github
30m 15s master
master
30m 15s
Do not use SingleProcced mode if STOC emulation is required. Build IGC #6808: Commit 53c3db5 pushed by VPG-SWE-Github
30m 30s master
master
30m 30s