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[Autobackout][FunctionalRegression]Revert of change: 4950fefed5b68f4d… Build IGC #6922: Commit 94adaee pushed by VPG-SWE-Github
30m 40s master
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Don't cast image args to 32-bit integers in built-ins PART#2 Build IGC #6921: Commit 4950fef pushed by VPG-SWE-Github
30m 7s master
master
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[Autobackout][FunctionalRegression]Revert of change: c5f774e4ee813208… Build IGC #6920: Commit 45bec13 pushed by VPG-SWE-Github
30m 8s master
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Add error when using wrong SIMD width Build IGC #6919: Commit 0801bfc pushed by VPG-SWE-Github
37m 19s master
master
37m 19s
builtin and intrinsic to disable IEEE exception trap bit in CR0 Build IGC #6918: Commit e88a6a7 pushed by VPG-SWE-Github
29m 46s master
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Debug and build options to enable IEEE float exception trap bit Build IGC #6917: Commit a97cf4a pushed by VPG-SWE-Github
30m 28s master
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30m 28s
Stale Pull Requests Stale Pull Requests #216: Scheduled
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Improve some 2dblock read Build IGC #6916: Commit 2fbb3b2 pushed by VPG-SWE-Github
30m 13s master
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30m 13s
Stale Pull Requests Stale Pull Requests #215: Scheduled
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Changes in code. Build IGC #6915: Commit b7b0543 pushed by VPG-SWE-Github
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Move lowering RayInfo to the RTBuilder Build IGC #6914: Commit fdde267 pushed by VPG-SWE-Github
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29m 49s
Update iSTD Hashing functions Build IGC #6913: Commit 9c5fdc5 pushed by VPG-SWE-Github
30m 15s master
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30m 15s
Stale Pull Requests Stale Pull Requests #214: Scheduled
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Fix coverity issue in VC Build IGC #6912: Commit 55ffa9c pushed by VPG-SWE-Github
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Enable drop to SIMD16 for XE3 Build IGC #6911: Commit 38cb5bc pushed by VPG-SWE-Github
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Simplification of DivergentBarrierPass constructor Build IGC #6910: Commit c5f774e pushed by VPG-SWE-Github
30m 22s master
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Need mov for small 2dblock read Build IGC #6909: Commit fcf28e9 pushed by VPG-SWE-Github
30m 4s master
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Move VRT GRF bump up after GRA optimizations Build IGC #6908: Commit cce99b4 pushed by VPG-SWE-Github
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Enable merging allocas for raytracing Build IGC #6907: Commit 5a8a083 pushed by VPG-SWE-Github
30m 22s master
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Stale Pull Requests Stale Pull Requests #213: Scheduled
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Changes in code. Build IGC #6906: Commit 6f4f144 pushed by VPG-SWE-Github
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Allocate whole GRF number for VC untyped load 2D intrinsics Build IGC #6905: Commit dce3951 pushed by VPG-SWE-Github
29m 24s master
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Replace a recursive algorithm to an iterative one Build IGC #6904: Commit 80f34b1 pushed by VPG-SWE-Github
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builtin and intrinsic to set IEEE exception trap bit in CR0 Build IGC #6903: Commit 5aaeb6b pushed by VPG-SWE-Github
29m 49s master
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Add support for Freeze instruction in WIAnalysis pass Build IGC #6902: Commit db79415 pushed by VPG-SWE-Github
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